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| Features * Incorporates the ARM7TDMITM ARM(R) Thumb(R) Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE (In Circuit Emulation) 4K Bytes Internal RAM Fully Programmable External Bus Interface (EBI) - Maximum External Address Space of 64M Bytes - Up to 8 Chip Selects - Software Programmable 8/16-bit External Databus 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 4 External interrupts, including a High-priority Low-latency Interrupt Request 32 Programmable I/O Lines 3-channel 16-bit Timer/Counter - 3 External Clock Inputs - 2 Multi-purpose I/O Pins per Channel 2 USARTs - 2 Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Low-power Idle Mode Fully Static Operation: 0 Hz to 33 MHz 2.7V to 3.6V Operating Range Available in a 100-lead TQFP Package * * * * * * * * * * * AT91 ARM(R) Thumb(R) Microcontrollers AT91M40400 1 Description The AT91M40400 is a member of the Atmel AT91 16/32-bit Microcontroller family which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91M40400 features a direct connection to off-chip memory, including Flash, through the fully programmable External Bus Interface (EBI). An eight-level priority vectored interrupt controller, in conjuction with the Peripheral Data Controller significantly improve the real-time performance of the device. The device is manufactured using Atmel's high density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip RAM and a wide range of peripheral functions on a monolithic chip, the Atmel AT91M40400 is a powerful microcontroller that offers a flexible, cost-effective solution to many compute-intensive embedded control applications. Rev. 0768C-10/99 1 Pin Configuration Figure 1. AT91M40400 Pinout (Top View) NWR0/NWE NWR1/NUB 77 P25/MCKO P27/NCS3 P26/NCS2 P22/RXD1 76 NRD/NOE NWDOVF P24/BMS NWAIT NRST 79 NCS1 NCS0 MCKI GND GND 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 100 78 GND TDO TMS VDD VDD VDD TCK P23 TDI A0/NLB GND A1 A2 A3 A4 A5 A6 A7 VDD A8 A9 A10 A11 A12 A13 A14 GND GND A15 A16 A17 A18 A19 P28/A20/CS7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 P21/TXD1/NTRI P20/SCK1 P19 P18 P17 P16 P15/RXD0 P14/TXD0 P13/SCK0 P12/FIQ GND P11/IRQ2 P10/IRQ1 VDD VDD P9/IRQ0 P8/TIOB2 P7/TIOA2 P6/TCLK2 P5/TIOB1 P4/TIOA1 P3/TCLK1 GND GND P2/TIOB0 AT91M40400 100-Lead TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P29/A21/CS6 P30/A22/CS5 2 AT91M40400 P31/A23/CS4 P0/TCLK0 P1/TIOA0 GND VDD VDD VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 AT91M40400 Table 1. AT91M40400 Pin Description Module Name A0-A23 D0-D15 NCS0-NCS3 CS4-CS7 NWR0 NWR1 EBI NRD NWE NOE NUB NLB NWAIT BMS FIQ AIC IRQ0-IRQ2 TCLK0-TCLK2 Timer TIOA0-TIOA2 TIOB0-TIOB2 SCK0-SCK1 USART TXD0-TXD1 RXD0-RXD1 PIO WD Clock MCKO NRST Reset NTRI TMS TDI ICE TDO TCK VDD Power GND Ground Ground -Test Data Output Test Clock Power Output Input Power ---Schmidt trigger, internal pull-up Tristate Mode Select Test Mode Select Test Data Input Input Input Input Low --Sampled during reset Schmidt trigger, internal pull-up Schmidt trigger, internal pull-up Master Clock Output Hardware Reset Input Output Input -Low Schmidt trigger, internal pull-up P0-P31 NWDOVF MCKI External Interrupt Request Timer External Clock Multipurpose Timer I/O pin A Multipurpose Timer I/O pin B External Serial Clock Transmit Data Output Receive Data Input Parallel IO line Watchdog overflow Master Clock Input Input Input I/O I/O I/O Output Input I/O Output Input --------Low -PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset See Table 8 Open-drain Schmidt trigger Function Address Bus Data Bus Chip Select Chip Select Lower Byte 0 Write Signal Upper Byte 1 Write Signal Read Signal Write Enable Output Enable Upper Byte Select Lower Byte Select Wait Input Boot Mode Select Fast Interrupt Request Type Output I/O Output Output Output Output Output Output Output Output Output Input Input Input Active Level --Low High Low Low Low Low Low Low Low Low --Sampled during reset PIO-controlled after reset A23-A20 after reset Used in Byte Write option Used in Byte Write option Used in Byte Write option Used in Byte Select option Used in Byte Select option Used in Byte Select option Used in Byte Select option Comments All valid after reset 3 Block Diagram Figure 2. AT91M40400 TMS TDO TDI TCK Reset NRST Embedded ICE D0-D15 ARM7TDMI Core ASB MCKI Clock P25/MCKO RAM 4K bytes EBI: External Bus Interface A1-A19 A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0 NCS1 P26/NCS2 P27/NCS3 P28/A20/CS7 P29/A21/CS6 P30/A22/CS5 P31/A23/CS4 P I O ASB Controller P I O AIC: Advanced Interrupt Controller AMBA Bridge EBI User Interface P12/FIQ P9/IRQ0 P10/IRQ1 P11/IRQ2 P13/SCK0 P14/TXD0 P15/RXD0 P20/SCK1 P21/TXD1/NTRI P22/RXD1 USART0 2 PDC Channels APB 2 PDC Channels TC: Timer Counter TC0 P0/TCLK0 P3/TCLK1 P6/TCLK2 P1/TIOA0 P2/TIOB0 P4/TIOA1 P5/TIOB1 P7/TIOA2 P8/TIOB2 USART1 TC1 TC2 PS: Power Saving P16 P17 P18 P19 P23 P24/BMS WD: Watchdog Timer NWDOVF Chip ID PIO: Parallel I/O Controller 4 AT91M40400 AT91M40400 Architectural Overview The AT91M40400 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and the on and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64k contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The AT91M40400 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has a 16K byte address space allocated in the upper 3M bytes of the 4G byte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modifywrite and complex bit manipulation instructions and without having to store-disable-restore the interrupt state. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O controller. The PIO controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO Controller in order to define which peripheral signals are connected with offchip logic. The ARM7TDMI processor operates in little-endian mode in the AT91M40400 microcontroller. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI Datasheet. The memory map and the on-chip peripherals are described in the subsequent sections of this datasheet. Electrical characteristics are documented in a separate datasheet entitled "AT91M40400 Electrical and Mechanical Characteristics". The ARM Standard In-Circuit-Emulation debug interface is supported via the ICE port of the AT91M40400 microcontroller. (This is not a standard IEEE 1149.1 JTAG Boundary Scan interface) PDC: Peripheral Data Controller The AT91M40400 has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART. The user interface of a PDC channel is integrated in the memory space of each USART channel. It contains a 32-bit address pointer register and a 16-bit byte count register. When the programmed number of bytes are transferred, an end of transfer interrupt is generated by the corresponding USART. See the section describing the USART beginning on page 64 for more details on PDC operation and programming. 5 Memory Map Figure 3. AT91M40400 0xFFFFFFFF Fixed Internal Area On-chip Peripherals 3M bytes 0xFFD00000 External Memory [7] 0xXXXFFFFF 0xXXX00000 Programmable Page Size 1, 4, 16 or 64 M bytes 0xXXXFFFFF External Memory [6] 0xXXX00000 Programmable Page Size 1, 4, 16 or 64 M bytes External Memory [5] 0xXXXFFFFF 0xXXX00000 Programmable Page Size 1, 4, 16 or 64 M bytes 0xXXXFFFFF External Memory [4] Programmable Base Address and Page Size 0xXXX00000 Programmable Page Size 1, 4, 16 or 64 M bytes External Memory [3] 0xXXXFFFFF 0xXXX00000 Programmable Page Size 1, 4, 16 or 64 M bytes External Memory [2] 0xXXXFFFFF 0xXXX00000 0xXXXFFFFF 0xXXX00000 Programmable Page Size 1, 4, 16 or 64 M bytes External Memory [1] Programmable Page Size 1, 4, 16 or 64 M bytes External Memory [0] 0xXXXFFFFF 0xXXX00000 Programmable Page Size 1, 4, 16 or 64 M bytes Remapping during BOOT On-chip RAM (during BOOT) Reserved On-chip Device Reserved On-chip Device On-chip RAM (normal) or BOOT Memory (during BOOT) 0x003FFFFF 0x00300000 0x002FFFFF 0x00200000 0x001FFFFF 0x00100000 0x000FFFFF 0x00000000 1M byte 1M byte 1M byte 1M byte Fixed Internal Area 6 AT91M40400 AT91M40400 Peripheral Memory Map Figure 4. AT91M40400 AIC: Advanced Interrupt Controller Reserved 0xFFFFBFFF WD: Watchdog Timer 0xFFFF8000 0xFFFF7FFF PS: Power Saving 0xFFFF4000 0xFFFF3FFF 0xFFFF0000 Reserved 0xFFFE3FFF 0xFFFE0000 Reserved 3M bytes USART 0 0xFFFD0000 0xFFFCFFFF USART 1 0xFFFCC000 Reserved 0xFFF03FFF SF: Special Function 0xFFF00000 Reserved 0xFFE03FFF EBI: External Bus Interface 0xFFE00000 Reserved 0xFFD00000 16K bytes 16K bytes 16K bytes 0xFFFD3FFF 16K bytes 16K bytes 16K bytes 0xFFFFFFFF 0xFFFFF000 4K bytes PIO: Parallel I/O Controller 16K bytes TC: Timer Counter 16K bytes 7 Initialization Reset Reset initializes the user interface registers to their default states as defined in the peripheral sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter the ARM core registers do not have defined reset states. When reset is active, the inputs of the AT91M40400 must be held at valid logic levels. The EBI address lines drive low during reset. Emulation Functions Tristate Mode The AT91M40400 provides a Tristate Mode, which is used for debug purposes in order to connect an emulator probe to an application board. In Tristate Mode the AT91M40400 continues to function, but all the output pin drivers are tristated. To enter Tristate Mode, the pin NTRI must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation the pin NTRI must be held high during reset, by a resistor of up to 400k ohm. NTRI must be driven to a valid logic value during reset. NTRI is multiplexed with Parallel I/O P21 and USART 1 serial data transmit line TXD1. Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is connected to one of these drivers this pull-up will ensure normal operation, without the need for an additional external resistor. NRST Pin NRST is the active low reset input. It is asserted asynchronously, but exit from reset is synchronized internally to MCKI. MCKI must be active within specification for a minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct operation. The pins BMS and NTRI are sampled during the 10 clock cycles just prior to the rising edge of NRST. Watchdog Reset The internally generated watchdog reset has the same effect as the NRST pin, except that the pins BMS and TRI are not sampled. Boot Mode and Tristate Mode are not updated. The NRST pin has priority if both types of reset coincide. JTAG/ICE Debug Mode ARM Standard Embedded In Circuit Emulation is supported via the JTAG/ICE port. It is connected to a host computer via an external ICE Interface. In ICE Debug Mode the ARM core responds with a nonJTAG chip ID which identifies the core to the ICE system. This is not IEEE 1149.1 JTAG compliant. Boot Mode Select The input level on the BMS pin during the last 10 clock cycles before the rising edge of NRST selects the type of Boot memory. Boot operation is described on page 13. BMS must be driven to a valid logic value during reset. The Boot Mode depends on BMS and whether the AT91M40400 has on-chip non-volatile memory (NVM). See Table 2 below. The correct logic level on BMS can be ensured with a resistor (pull-up or pull-down). See "AT91M40400 Electrical and Mechanical Characteristics" for the resistor value specification. The BMS pin is multiplexed with Parallel I/O P24 which can be programmed after reset like any standard PIO. Table 2. Boot Mode Select BMS 1 NVM on-chip 0 All Internal 32-bit NVM External 16-bit memory on NCS0 Architecture No NVM Boot Mode External 8-bit memory on NCS0 8 AT91M40400 AT91M40400 EBI: External Bus Interface The EBI generates the signals which control the access to the external memory or peripheral devices. The EBI is fully programmable and can address up to 64M bytes. It has eight chip selects and a 24-bit address bus, the upper four bits of which are multiplexed with a chip select. The 16-bit data bus can be configured to interface with 8or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols allowing single clock cycle memory accesses. The main features are: * External Memory Mapping * Up to 8 chip select lines * 8- or 16-bit data bus * Byte write or byte select lines * Remap of boot memory * Two different read protocols * Programmable wait state generation * External wait request * Programmable data float time The EBI User Interface is described on page 30. Figure 5. External Memory Smaller than Page Size Base + 4M byte 1M byte device Hi Low Base + 3M byte 1M byte device Memory Map 1M byte device Hi Low Base + 2M byte Hi Low Base + 1M byte 1M byte device Hi Low Base Repeat 1 Repeat 2 Repeat 3 External Memory Mapping The memory map associates the internal 32-bit address space with the external 24-bit address bus. The memory map is defined by programming the base address and page size of the external memories (see EBI User Interface registers EBI_CSR0 to EBI_CSR7). Note that A0-A23 is only significant for 8-bit memory; A1-A23 is used for 16-bit memory. If the physical memory device is smaller than the programmed page size, it wraps around and appears to be repeated within the page. The EBI correctly handles any valid access to the memory device within the page (see Figure 5). In the event of an access request to an address outside any programmed page, an Abort signal is generated. Two types of Abort are possible: instruction prefetch abort and data abort. The corresponding exception vector addresses are respectively 0x0000000C and 0x00000010. It is up to the system programmer to program the error handling routine to use in case of an Abort (see the ARM7TDMI Datasheet for further information). 9 Pin Description Name A0 - A23 D0 - D15 NCS0 - NCS3 CS4 - CS7 NRD NWR0 - NWR1 NOE NWE NUB, NLB NWAIT Description Address bus (output) Data bus (input/output) Active low chip selects (output) Active high chip selects (output) Read Enable (output) Lower and upper write enable (output) Output enable (output) Write enable (output) Upper and lower byte select (output) Wait request (input) Type Output I/O Output Output Output Output Output Output Output Input The following table shows how certain EBI signals are multiplexed: Multiplexed Signals A23 - A20 A0 NRD NWR0 NWR1 CS4 - CS7 NLB NOE NWE NUB Functions Allows from 4 to 8 chip select lines to be used. 8- or 16-bit data bus Byte-write or byte select access Byte-write or byte select access Byte-write or byte select access 10 AT91M40400 AT91M40400 Chip Select Lines The EBI provides up to eight chip select lines: * Chip select lines NCS0 - NCS3 are dedicated to the EBI (not multiplexed). * Chip select lines CS4 - CS7 are multiplexed with the top four address lines A23 - A20. By exchanging address lines for chip select lines, the user can optimize the EBI to suit his external memory requirements: more external devices or larger address range for each device. The selection is controlled by the ALE field in EBI_MCR (Memory Control Register). The following combinations are possible: A20, A21, A22, A23 (configuration by default) A20, A21, A22, CS4 A20, A21, CS5, CS4 A20, CS6, CS5, CS4 CS7, CS6, CS5, CS4 Figure 6. Memory Connections for Four External Devices NCS0 - NCS3 NRD EBI NWRx A0 - A23 D0 - D15 NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A0 - A23 8 or 16 D0 - D15 or D0 - D7 Note: 1. For four external devices, the maximum address space per device is 16M bytes. Figure 7. Memory Connections for Eight External Devices CS4 - CS7 NCS0 - NCS3 NRD EBI NWRx A0 - A19 D0 - D15 CS7 CS6 CS5 CS4 NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A0 - A19 8 or 16 D0 - D15 or D0 - D7 Note: 1. For eight external devices, the maximum address space per device is 1M byte. 11 Data Bus Width A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the DBW field in the EBI_CSR (Chip Select Register) for the corresponding chip select. Figure 8 shows how to connect a 512K x 8-bit memory on NCS2. Figure 8. Memory Connection for an 8-Bit Data Bus D0 - D7 D8 - D15 A1 - A18 EBI A0 NWR1 NWR0 NRD NCS2 Write Enable Output Enable Memory Enable A1 - A18 A0 D0 - D7 Byte Write or Byte Select Access Each chip select with a 16-bit data bus can operate with one of two different types of write access: * Byte Write Access supports two byte write and a single read signal. * Byte Select Access selects upper and/or lower byte with two byte select lines, and separate read and write signals. This option is controlled by the BAT field in the EBI_CSR (Chip Select Register) for the corresponding chip select. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory page. * The signal A0/NLB is not used. * The signal NWR1/NUB is used as NWR1 and enables upper byte writes. * The signal NWR0/NWE is used as NWR0 and enables lower byte writes. * The signal NRD/NOE is used as NRD and enables halfword and byte reads. Figure 10 shows how to connect two 512K x 8-bit devices in parallel on NCS2. Figure 10. Memory Connection for 2 x 8-Bit Data Busses D0 - D7 D8 - D15 EBI A1 - A19 A0 NWR1 NWR0 NRD NCS2 Write Enable Read Enable Memory Enable A0 - A18 D0 - D7 Figure 9 shows how to connect a 512K x 16-bit memory on NCS2. Figure 9. Memory Connection for a 16-Bit Data Bus D0 - D7 D8 - D15 EBI A1 - A19 NLB NUB NWE NOE NCS2 D0 - D7 D8 - D15 A0 - A18 Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable D8 - D15 A0 - A18 Write Enable Read Enable Memory Enable Byte Select Access is used to connect 16-bit devices in a memory page. * The signal A0/NLB is used as NLB and enables the lower byte for both read and write operations. * The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write operations. 12 AT91M40400 AT91M40400 The signal NWR0/NWE is used as NWE and enables writing for byte or half word. * The signal NRD/NOE is used as NOE and enables reading for byte or half word. Figure 11 shows how to connect a 16-bit device with byte and half word access (e.g. 16-bit SRAM) on NCS2. * Boot Conventional program operation requires RAM memory at page zero to support dynamic exception vectors. However it is necessary to boot from non-volatile memory at page zero. When the AT91M40400 is reset, the memory map is modified to place NVM at page zero. The on-chip RAM is remapped to address 0x00300000 and either on-chip 32-bit NVM or off-chip 8/16-bit NVM is remapped to address 0x00000000. The off-chip NVM is selected on NCS0. The Boot memory type is selected by the BMS pin when NRST is active (see Boot Mode Select on page 8). Watchdog reset does not change the Boot memory selection but does perform a full reboot from the previously selected memory. The memory map is returned to its conventional configuration by writing 1 to the RCB bit of the EBI_RCR (Remap Control Register). This cancels the remapping and enables normal operation of the EBI, as programmed (see page 33). It is not possible to remap the memory by writing 0 to the RCB bit in EBI_RCR. During Boot the number of external devices (number of active chip selects) and their configurations must be programmed as described in the EBI User Interface (see page 30). The chip select addresses which are programmed take effect when memory remapping is cancelled. Only NCS0 is active while the memory is remapped. Wait states take effect immediately when they are programmed to allow Boot program execution to be optimized. Figure 11. Connection for a 16-Bit Data Bus with byte and half word access D0 - D7 D8 - D15 EBI A1 - A19 NLB NUB NWE NOE NCS2 D0 - D7 D8 - D15 A0 - A18 Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable Figure 12 shows how to connect a 16-bit device without byte access (e.g. Flash) on NCS2. Figure 12. Connection for a 16-Bit Data Bus Without Byte Write Capability. D0 - D7 D8 - D15 EBI A1 - A19 NLB NUB NWE NOE NCS2 Write Enable Output Enable Memory Enable D0 - D7 D8 - D15 A0 - A18 13 Read Protocols The EBI provides two alternative protocols for external memory read access: standard and early read. The difference between the two protocols lies in the timing of the NRD (read cycle) waveform. The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is valid for all memory devices. Standard read protocol is the default protocol after reset. Note: In the following waveforms and descriptions, NRD represents NRD and NOE since the two signals have the same waveform. Likewise, NWE represents NWE, NWR0 and NWR1 unless NWR0 and NWR1 are otherwise represented. ADDR represents A0-A23 and/or A1-A23. Standard Read Protocol Standard read protocol implements a read cycle in which NRD and NWE are similar. Both are active during the second half of the clock cycle. The first half of the clock cycle allows time to ensure completion of the previous access as well as the output of address and NCS before the read cycle begins. During a standard read protocol external memory access, NCS is set low and ADDR is valid at the beginning of the access while NRD goes low only in the second half of the master clock cycle to avoid bus conflict (see Figure 13). NWE is the same in both protocols. NWE always goes low in the second half of the master clock cycle (see Figure 14). Early Read Protocol Early read protocol provides more time for a read access from the memory by asserting NRD at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NRD remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol can allow a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contentions on the external bus. Early Read Wait State In early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins (see Figure 15). This wait state is generated in addition to any other programmed wait states (i.e. data float wait). No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. Early read wait states affect the external bus only. They do not affect internal bus timing. Figure 13. Standard Read Protocol MCKI ADDR NCS NRD or NWE Figure 14. Early Read Protocol MCKI ADDR NCS NRD or NWE Figure 15. Early Read Wait State write cycle MCKI early read wait read cycle ADDR NCS NRD NWE 14 AT91M40400 AT91M40400 Write Data Hold Time During write cycles in both protocols, output data becomes valid after the falling edge of the NWE signal and remains valid after the rising edge of NWE, as illustrated in the figure below. The external NWE waveform (on the NWE pin) is used to control the output data timing to guarantee this operation. It is therefore necessary to avoid excessive loading of the NWE pins, which could delay the write signal too long and cause a contention with a subsequent read cycle in standard protocol. Figure 16. Data Hold Time MCKI Wait States The EBI can automatically insert wait states. The different types of wait states are listed below: * Standard wait states * Data float wait states * External wait states * Chip select change wait states * Early Read wait states (as described in Read Protocols) Standard Wait States Each chip select can be programmed to insert one or more wait states during an access on the corresponding device. This is done by setting the WSE field in the corresponding EBI_CSR. The number of cycles to insert is programmed in the NWS field in the same register. Below is the correspondence between the number of standard wait states programmed and the number of cycles during which the NWE pulse is held low: 0 wait states 1/2 cycle 1 wait state 1 cycle For each additional wait state programmed, an additional cycle is added. Figure 17. One Wait State access ADDR NWE Data output In early read protocol the data can remain valid longer than in standard read protocol due to the additional wait cycle which follows a write access. 1 wait state access MCKI ADDR NCS NWE NRD (1) (2) Notes: 1. 2. Early Read Protocol Standard Read Protocol 15 Data Float Wait State Some memory devices are slow to release the external bus. For such devices it is necessary to add wait states (data float waits) after a read access before starting a write access or a read access to a different external memory. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF field of the EBI_CSR register for the corresponding chip select. The value (0-7 clock cycles) indicates the number of data float waits to be inserted and represents the time allowed for the data output to go high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence a single access to an external memory with long tDF will not slow down the execution of a program from internal memory. The EBI keeps track of the programmed external data float time during internal accesses, to ensure that the external memory system is not accessed while it is still busy. Figure 18. Data Float Output Time External Wait The NWAIT input can be used to add wait states at any time. NWAIT is active low and is detected on the rising edge of the clock. If NWAIT is low at the rising edge of the clock, the EBI adds a wait state and changes neither the output signals nor its internal counters and state. When NWAIT is de-asserted, the EBI finishes the access sequence. Figure 19. External Wait MCKI ADDR NWAIT NCS MCKI NWE ADDR NRD (1) (2) NCS Notes: NRD (1) (2) tDF D0-D15 1. 2. Early Read Protocol Standard Read Protocol The NWAIT signal must meet setup and hold requirements on the rising edge of the clock. Notes: 1. 2. Early Read Protocol Standard Read Protocol Internal memory accesses and consecutive accesses to the same external memory do not have added Data Float wait states. 16 AT91M40400 AT91M40400 Chip Select Change Wait States A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no wait states have already been inserted). If any wait states have already been inserted, (e.g. data float wait) then none are added. Figure 20. Chip Select Wait mem 1 MCKI chip select wait mem 2 NCS 1 NCS 2 NRD (1) (2) NWE Notes: 1. 2. Early Read Protocol Standard Read Protocol 17 Memory Access Waveforms Figures 21 through 24 show examples of the two alternative protocols for external memory read access. Figure 21. Standard Read Protocol with no tDF read mem 2 read mem 2 write mem 2 read mem 1 chip select change wait read mem 1 write mem 1 MCKI NWE NCS 1 A0-A23 NCS 2 NRD D0-D15 (AT91) tWHDX D0-D15 (Mem 2) D0-D15 (Mem1) 18 AT91M40400 tWHDX Figure 22. Early Read Protocol with no tDF read mem 1 MCKI write mem 1 early read wait cycle read mem 1 read mem 2 write mem 2 early read wait cycle read mem 2 A0-A23 NRD NWE NCS 1 chip select change wait NCS 2 D0-D15 (Mem 1) D0-D15 (AT91) long tWHDX D0-D15 (Mem 2) long tWHDX AT91M40400 19 Figure 23. Standard Read Protocol with tDF 20 read mem 1 data float wait MCKI write mem 1 read mem 1 data float wait read mem 2 read mem 2 data float wait write mem 2 write mem 2 write mem 2 AT91M40400 A0-A23 NRD NWE NCS 1 NCS 2 tDF D0-D15 (Mem 1) tDF D0-D15 (AT91) tWHDX D0-D15 (Mem 2) tDF Figure 24. Early Read Protocol with tDF read mem 1 data float wait MCKI write mem 1 early read wait read mem 1 data float wait read mem 2 read mem 2 data float wait write mem 2 write mem 2 write mem 2 A0-A23 NRD NWE NCS 1 NCS 2 tDF D0-D15 (Mem 1) tDF D0-D15 (AT91) AT91M40400 tWHDX D0-D15 (Mem 2) tDF 21 Figures 25 through 31 show the timing cycles and wait states for read and write access to the various AT91M40400 external memory devices. The configurations described are as follows: Table 3. Memory Access Waveforms Figure Number 25 26 27 28 29 30 31 Number of Wait States 0 1 1 0 1 1 0 Bus Width 16 16 16 8 8 8 16 Size of Data Transfer Word Word Half Word Word Half Word Byte Byte 22 AT91M40400 AT91M40400 Figure 25. 0 Wait States, 16-Bit Bus Width, Word Transfer MCKI A1-A23 ADDR ADDR+1 NCS NLB NUB READ ACCESS * Standard Protocol NRD D0-D15 B2 B1 B 4 B3 Internal Bus X X B 2 B1 B4 B 3 B 2 B 1 * Early Protocol NRD D0-D15 B 2 B1 B 4 B3 WRITE ACCESS * Byte Write/ Byte Select Option NWE D0-D15 B 2 B1 B 4 B3 23 Figure 26. 1 Wait, 16-Bit Bus Width, Word Transfer 1 wait state MCKI 1 wait state A1-A23 ADDR ADDR+1 NCS NLB NUB Read Access * Standard Protocol NRD D0-D15 B2 B1 B 4 B3 Internal Bus X X B2 B1 B4 B 3 B 2 B 1 * Early Protocol NRD D0-D15 B2 B1 B4 B3 Write Access * Byte Write/ Byte Select Option NWE D0-D15 B 2 B1 B4 B3 24 AT91M40400 AT91M40400 Figure 27. 1 Wait State, 16-Bit Bus Width, Half Word Transfer 1 wait state MCKI A1-A23 NCS NLB NUB READ ACCESS * Standard Protocol NRD D0-D15 B2 B 1 Internal Bus X X B 2 B1 * Early Protocol NRD D0-D15 WRITE ACCESS B2 B1 * Byte Write/ Byte Select Option NWE D0-D15 B 2 B1 25 Figure 28. 0 Wait States, 8-Bit Bus Width, Word Transfer MCKI A0-A23 ADDR ADDR+1 ADDR+2 ADDR+3 NCS READ ACCESS * Standard Protocol NRD D0-D15 X B1 X B2 X B3 X B4 Internal Bus X X X B1 X X B 2 B1 X B 3 B2 B 1 B4 B 3 B 2 B 1 * Early Protocol NRD D0-D15 X B1 X B2 X B3 X B4 WRITE ACCESS NWR0 NWR1 D0-D15 X B1 X B2 X B3 X B4 26 AT91M40400 AT91M40400 Figure 29. 1 Wait State, 8-Bit Bus Width, Half Word Transfer 1 wait state MCKI 1 wait state A0-A23 ADDR ADDR+1 NCS READ ACCESS * Standard Protocol NRD D0-D15 X B1 X B2 Internal Bus X X X B1 X X B 2 B1 * Early Protocol NRD D0-D15 WRITE ACCESS X B1 X B2 NWR0 NWR1 D0-D15 X B1 X B2 27 Figure 30. 1 Wait State, 8-Bit Bus Width, Byte Transfer 1 wait state MCKI A0-A23 NCS READ ACCESS * Standard Protocol NRD D0-D15 XB1 Internal Bus X X X B1 * Early Protocol NRD D0-D15 WRITE ACCESS X B1 NWR0 NWR1 D0-D15 X B1 28 AT91M40400 AT91M40400 Figure 31. 0 Wait States, 16-Bit Bus Width, Byte Transfer MCKI A1-A23 ADDR X X X 0 ADDR X X X 0 Internal Address ADDR X X X 0 ADDR X X X 1 NCS NLB NUB READ ACCESS * Standard Protocol NRD D0-D15 X B1 B2X Internal Bus X X X B1 X X B2X * Early Protocol NRD D0-D15 WRITE ACCESS XB1 B2X * Byte Write Option NWR0 NWR1 D0-D15 B1B1 B2B2 * Byte Select Option NWE 29 EBI User Interface The EBI is programmed using the registers listed in the table below. The Remap Control Register (EBI_RCR) controls exit from Boot Mode (See "Boot" on page 13.) The Memory Control Register (EBI_MCR) is used to program the number of active chip selects and data read protocol. Base Address: 0xFFE00000 Table 4. EBI Memory Map Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 Notes: 1. 2. Register Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Chip Select Register 4 Chip Select Register 5 Chip Select Register 6 Chip Select Register 7 Remap Control Register Memory Control Register 8-Bit boot (if BMS is detected high) 16-Bit boot (if BMS is detected low) Name EBI_CSR0 EBI_CSR1 EBI_CSR2 EBI_CSR3 EBI_CSR4 EBI_CSR5 EBI_CSR6 EBI_CSR7 EBI_RCR EBI_MCR Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write only Read/Write Reset State 0x0000203E (1) 0x0000203D (2) 0x10000000 0x20000000 0x30000000 0x40000000 0x50000000 0x60000000 0x70000000 - 0 Eight Chip Select Registers (EBI_CSR0 to EBI_CSR7) are used to program the parameters for the individual external memories. Each EBI_CSR must be programmed with a different base address, even for unused chip selects. 30 AT91M40400 AT91M40400 EBI Chip Select Register Register Name: Access Type: Reset Value: Absolute Address: 31 EBI_CSR0 - EBI_CSR7 Read/Write See Table 4 0xFFE00000 - 0xFFE0001C 30 29 28 BA 27 26 25 24 23 22 BA 21 20 19 -- 18 -10 TDF 17 -9 16 -8 PAGES 15 -7 PAGES 14 -6 -- 13 CSEN 5 WSE 12 BAT 4 11 3 NWS 2 1 DBW 0 * DBW: Data Bus Width DBW 0 0 1 1 0 1 0 1 Data Bus Width Reserved 16-bit data bus width 8-bit data bus width Reserved * NWS: Number of Wait States This field is valid only if WSE is set. NWS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Number of Standard Wait States 1 2 3 4 5 6 7 8 * WSE: Wait State Enable 0 = Wait state generation is disabled. No wait states are inserted. 1 = Wait state generation is enabled. 31 * PAGES: Page Size PAGES 0 0 1 1 0 1 0 1 Page Size 1M byte 4M bytes 16M bytes 64M bytes Active bits in base address 12 bits (31-20) 10 bits (31-22) 8 bits (31-24) 6 bits (31-26) * TDF: Data Float Output Time TDF 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Number of Cycles added after the transfer 0 1 2 3 4 5 6 7 * * * BAT: Byte Access Type 0 = Byte write access type. 1 = Byte select access type. CSEN: Chip Select Enable 0 = Chip select is disabled. 1 = Chip select is enabled. BA: Base Address These bits contain the highest bits of the base address. If the page size is larger than 1Mbyte, the unused bits of the base address are ignored by the EBI decoder. 32 AT91M40400 AT91M40400 EBI Remap Control Register Register Name: EBI_RCR Access Type: Write only Absolute Address: 0xFFE00020 31 --23 --15 --7 --30 --22 --14 --6 --29 --21 --13 --5 --28 --20 --12 --4 --27 --19 --11 --3 --26 --18 --10 --2 --25 --17 --9 --1 --24 --16 --8 --0 RCB * RCB: Remap Command Bit 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices. EBI Memory Control Register Register Name: Access Type: Reset Value: Absolute Address: 31 --23 --15 --7 --- EBI_MCR Read/Write See Table 4 0xFFE00024 30 --22 --14 --6 --29 --21 --13 --5 --28 --20 --12 --4 DRP 27 --19 --11 --3 --26 --18 --10 --2 25 --17 --9 --1 ALE 24 --16 --8 --0 * ALE: Address Line Enable This field determines the number of valid address lines and the number of valid chip select lines. ALE 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 Valid Address Bits A20, A21, A22, A23 A20, A21, A22 A20, A21 A20 none Maximum Addressable Space 16M bytes 8M bytes 4M bytes 2M bytes 1M bytes Valid Chip Select none CS4 CS4, CS5 CS4, CS5, CS6 CS4, CS5, CS6, CS7 * DRP: Data Read Protocol 0 = Standard read protocol for all external memory devices enabled. 1 = Early read protocol for all external memory devices enabled. 33 AIC: Advanced Interrupt Controller The AT91M40400 has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor's NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ2. The 8-level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high or low level sensitive. The interrupt sources are listed in Table 5 and the AIC programmable registers in Table 6. Figure 32. Interrupt Controller Block Diagram FIQ Source Memorization NFIQ Manager NFIQ Advanced Peripheral Bus (APB) Control Logic ARM7TDMI Core Internal Interrupt Sources External Interrupt Sources Memorization Priority Controller NIRQ Manager NIRQ Note: After a hardware reset, the AIC pins are controlled by the PIO Controller. They must be configured to be controlled by the peripheral before being used. 34 AT91M40400 AT91M40400 Table 5. AIC Interrupt Sources Interrupt Source 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Note: 1. Interrupt Name FIQ SWIRQ US0IRQ US1IRQ TC0IRQ TC1IRQ TC2IRQ WDIRQ PIOIRQ --------------IRQ0 IRQ1 IRQ2 --------------------------Interrupt Description Fast Interrupt Software Interrupt USART Channel 0 interrupt USART Channel 1 interrupt Timer Channel 0 interrupt Timer Channel 1 interrupt Timer Channel 2 interrupt Watchdog interrupt Parallel I/O Controller interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved External interrupt 0 External interrupt 1 External interrupt 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved interrupt sources are not available. Corresponding registers must not be used and read 0. 35 Hardware Interrupt Vectoring The hardware interrupt vectoring reduces the number of instructions to reach the interrupt handler to only one. By storing the following instruction at address 0x00000018, the processor loads the program counter with the interrupt handler address stored in the AIC_IVR register. Execution is then vectored to the interrupt handler corresponding to the current interrupt. ldr PC,[PC,# -&F20] The current interrupt is the interrupt with the highest priority when the Interrupt Vector Register (AIC_IVR) is read. The value read in the AIC_IVR corresponds to the address stored in the Source Vector Register (AIC_SVR) of the current interrupt. Each interrupt source has its corresponding AIC_SVR. In order to take advantage of the hardware interrupt vectoring it is necessary to store the address of each interrupt handler in the corresponding AIC_SVR, at system initialization. Interrupt Handling The interrupt handler must read the AIC_IVR as soon as possible. This de-asserts the NIRQ request to the processor and clears the interrupt in case it is programmed to be edge triggered. This permits the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs. At the end of the interrupt service routine, the end of interrupt command register (AIC_EOICR) must be written. This allows pending interrupts to be serviced. Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled using the command registers AIC_IECR and AIC_IDCR. The interrupt mask can be read in the read only register AIC_IMR. A disabled interrupt does not affect the servicing of other interrupts. Interrupt Clearing and Setting All interrupt sources which are programmed to be edge triggered (including FIQ) can be individually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR. This function of the interrupt controller is available for auto-test or software debug purposes. Priority Controller The NIRQ line is controlled by an 8-level priority encoder. Each source has a programmable priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest. When the AIC receives more than one unmasked interrupt at a time, the interrupt with the highest priority is serviced first. If both interrupts have equal priority, the interrupt with the lowest interrupt source number (see table 5) is serviced first. The current priority level is defined as the priority level of the current interrupt at the time the register AIC_IVR is read (the interrupt which will be serviced). In the case when a higher priority unmasked interrupt occurs while an interrupt already exists, there are two possible outcomes depending on whether the AIC_IVR has been read. * If the NIRQ line has been asserted but the AIC_IVR has not been read, then the processor will read the new higher priority interrupt handler address in the AIC_IVR register and the current interrupt level is updated. * If the processor has already read the AIC_IVR then the NIRQ line is reasserted. When the processor has authorized nested interrupts to occur and reads the AIC_IVR again, it reads the new, higher priority interrupt handler address. At the same time the current priority value is pushed onto a first-in last-out stack and the current priority is updated to the higher priority. When the end of interrupt command register (AIC_EOICR) is written the current interrupt level is updated with the last stored interrupt level from the stack (if any). Hence at the end of a higher priority interrupt, the AIC returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted. Fast Interrupt Request The external FIQ line is the only source which can raise a fast interrupt request to the processor. Therefore it has no priority controller. The external FIQ line can be programmed to be positive or negative edge triggered or high or low level sensitive in the AIC_SMR0 register. The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written into this register is available by reading the AIC_FVR register when an FIQ interrupt is raised. By storing the following instruction at address 0x0000001C, the processor will load the program counter with the interrupt handler address stored in the AIC_FVR register. ldr PC,[PC,# -&F20] Alternatively the interrupt handler can be stored starting from address 0x0000001C as described in the ARM7TDMI datasheet. Software Interrupt Interrupt source 1 of the advanced interrupt controller is a software interrupt. It must be programmed to be edge triggered in order to set or clear it by writing to the AIC_ISCR and AIC_ICCR. This is totally independent of the SWI instruction of the ARM7TDMI processor. 36 AT91M40400 AT91M40400 Spurious Interrupt When the AIC asserts the NIRQ line, the ARM7TDMI enters IRQ mode and the interrupt handler reads the IVR. It may happen that the AIC de-asserts the NIRQ line after the core has taken into account the NIRQ assertion and before the read of the IVR. This behavior is called a Spurious Interrupt. The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector when the IVR is read. The Spurious Vector can be programmed by the user when the vector table is initialized. A spurious interrupt may occur in the following cases: * With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is de-asserted at the same time as it is taken into account by the ARM7TDMI. * If an interrupt is asserted at the same time as the software is disabling the corresponding source through AIC_IDCR (this can happen due to the pipelining of the ARM core). The same mechanism of spurious interrupt occurs if the ARM7TDMI reads the IVR (application software or ICE) when there is no interrupt pending. This mechanism is also valid for the FIQ interrupts. Once the AIC enters the spurious interrupt management, it asserts neither the NIRQ nor the NFIQ lines to the ARM7TDMI as long as the spurious interrupt is not acknowledged. Therefore, it is mandatory for the Spurious Interrupt Service Routine to acknowledge the "spurious" behavior by writing to the AIC_EOICR (End of Interrupt) before returning to the interrupted software. It also can perform other operation(s), e.g. trace possible undesirable behavior. The Protect Mode is enabled by setting the AIC bit in the SF Protect Mode Register (see SF: Special Function Registers on page 145). When Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when IVR is written. An AIC_IVR read on its own (e.g. by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads performed in between the read and the write can cause unpredictable results. Therefore, it is strongly recommended not to set a breakpoint between these 2 actions, nor to stop the software. The debug system must not write to the AIC_IVR as this would cause undesirable effects. The following table shows the main steps of an interrupt and the order in which they are performed according to the mode: Action Calculate active interrupt (higher than current or spurious) Determine and return the vector of the active interrupt Memorize interrupt Push on internal stack the current priority level Acknowledge the interrupt No effect (2) Notes: (1) Normal Mode Read AIC_IVR Read AIC_IVR Read AIC_IVR Read AIC_IVR Read AIC_IVR Write AIC_IVR Protect Mode Read AIC_IVR Read AIC_IVR Read AIC_IVR Write AIC_IVR Write AIC_IVR --- Protect Mode The Protect Mode permits reading of the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a Debug Monitor or an ICE reads the AIC User Interface, the IVR could be read. This would have the following consequences in normal mode: * If an enabled interrupt with a higher priority than the current one is pending, it would be stacked. * If there is no enabled pending interrupt, the spurious vector would be returned. In either case, an End of Interrupt Command would be necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system. Hence the debug system would become strongly intrusive, and could cause the application to enter an undesired state. This is avoided by using Protect Mode. 1. NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level sensitive 2. Note that software which has been written and debugged using Protect Mode will run correctly in Normal Mode without modification. However in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. 37 AIC User Interface Base Address: 0xFFFFF000 Table 6. AIC Memory Map Offset 0x000 0x004 - 0x07C 0x080 0x084 - 0x0FC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 Note: 1. Register Source Mode Register 0 Source Mode Register 1 - Source Mode Register 31 Source Vector Register 0 Source Vector Register 1 - Source Vector Register 31 IRQ Vector Register FIQ Vector Register Interrupt Status Register Interrupt Pending Register Interrupt Mask Register Core Interrupt Status Register Reserved Reserved Interrupt Enable Command Register Interrupt Disable Command Register Interrupt Clear Command Register Interrupt Set Command Register End of Interrupt Command Register Spurious Vector Register Name AIC_SMR0 AIC_SMR1 - AIC_SMR31 AIC_SVR0 AIC_SVR1 - AIC_SVR31 AIC_IVR AIC_FVR AIC_ISR AIC_IPR AIC_IMR AIC_CISR - - AIC_IECR AIC_IDCR AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read only Read only Read only Read only Read only Read only - - Write only Write only Write only Write only Write only Read/Write Reset State 0 0 0 0 0 0 0 0 0 0 0 (see Note 1) 0 0 - - - - - - - 0 The reset value of this register depends on the level of the External IRQ lines. All other sources are cleared at reset. 38 AT91M40400 AT91M40400 AIC Source Mode Register Register Name: Access Type: Reset Value: 31 --23 --15 --7 --- AIC_SMR0 - AIC_SMR31 Read/Write 0 30 --22 --14 --6 SRCTYPE 29 --21 --13 --5 28 --20 --12 --4 --27 --19 --11 --3 --26 --18 --10 --2 25 --17 --9 --1 PRIOR 24 --16 --8 --0 * * PRIOR: Priority Level Program the priority level for all sources except source 0 (FIQ). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ, in the SMR0. SRCTYPE: Interrupt Source Type Program the input to be positive or negative edge triggered or positive or negative level sensitive. The active level or edge is not programmable for the internal sources. SRCTYPE 0 0 1 1 0 1 0 1 Internal Sources Level Sensitive Edge Triggered Level Sensitive Edge Triggered External Sources Low Level Sensitive Negative Edge Triggered High Level Sensitive Positive Edge Triggered 39 AIC Source Vector Register Register Name: Access Type: Reset Value: 31 AIC_SVR0 - AIC_SVR31 Read/Write 0 30 29 28 VECTOR 27 26 25 24 23 22 21 20 VECTOR 19 18 17 16 15 14 13 12 VECTOR 11 10 9 8 7 6 5 4 VECTOR 3 2 1 0 * VECTOR: Interrupt Handler Address The user may store in these registers the addresses of the corresponding handler for each interrupt source. 40 AT91M40400 AT91M40400 AIC Interrupt Vector Register Register Name: Access Type: Reset Value: 31 AIC_IVR Read only 0 30 29 28 IRQV 27 26 25 24 23 22 21 20 IRQV 19 18 17 16 15 14 13 12 IRQV 11 10 9 8 7 6 5 4 IRQV 3 2 1 0 * IRQV: Interrupt Vector Register The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register (1 to 31) is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the IRQ Vector Register reads 0. AIC FIQ Vector Register Register Name: Access Type: Reset Value: 31 AIC_FVR Read only 0 30 29 28 FIQV 27 26 25 24 23 22 21 20 FIQV 19 18 17 16 15 14 13 12 FIQV 11 10 9 8 7 6 5 4 FIQV 3 2 1 0 * FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0 which corresponds to FIQ. 41 AIC Interrupt Status Register Register Name: Access Type: Reset Value: 31 --23 --15 --7 --- AIC_ISR Read only 0 30 --22 --14 --6 --29 --21 --13 --5 --28 --20 --12 --4 27 --19 --11 --3 26 --18 --10 --2 IRQID 25 --17 --9 --1 24 --16 --8 --0 * IRQID: Current IRQ Identifier The Interrupt Status Register returns the current interrupt source number. 42 AT91M40400 AT91M40400 AIC Interrupt Pending Register Register Name: Access Type: Reset Value: 31 --23 --15 --7 WDIRQ AIC_IPR Read only 0 30 --22 --14 --6 TC2IRQ 29 --21 --13 --5 TC1IRQ 28 --20 --12 --4 TC0IRQ 27 --19 --11 --3 US1IRQ 26 --18 IRQ2 10 --2 US0IRQ 25 --17 IRQ1 9 --1 SWIRQ 24 --16 IRQ0 8 PIOIRQ 0 FIQ * Interrupt Pending 0 = Corresponding interrupt is inactive. 1 = Corresponding interrupt is pending. AIC Interrupt Mask Register Register Name: Access Type: Reset Value: 31 --23 --15 --7 WDIRQ AIC_IMR Read only 0 30 --22 --14 --6 TC2IRQ 29 --21 --13 --5 TC1IRQ 28 --20 --12 --4 TC0IRQ 27 --19 --11 --3 US1IRQ 26 --18 IRQ2 10 --2 US0IRQ 25 --17 IRQ1 9 --1 SWIRQ 24 --16 IRQ0 8 PIOIRQ 0 FIQ * Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. 43 AIC Core Interrupt Status Register Register Name: Access Type: Reset Value: 31 --23 --15 --7 --- AIC_CISR Read only 0 30 --22 --14 --6 --29 --21 --13 --5 --28 --20 --12 --4 --27 --19 --11 --3 --26 --18 --10 --2 --25 --17 --9 --1 NIRQ 24 --16 --8 --0 NFIQ * * NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active. NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active. 44 AT91M40400 AT91M40400 AIC Interrupt Enable Command Register Register Name: Access Type: 31 --23 --15 --7 WDIRQ AIC_IECR Write only 30 --22 --14 --6 TC2IRQ 29 --21 --13 --5 TC1IRQ 28 --20 --12 --4 TC0IRQ 27 --19 --11 --3 US1IRQ 26 --18 IRQ2 10 --2 US0IRQ 25 --17 IRQ1 9 --1 SWIRQ 24 --16 IRQ0 8 PIOIRQ 0 FIQ * Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt. AIC Interrupt Disable Command Register Register Name: Access Type: 31 --23 --15 --7 WDIRQ AIC_IDCR Write only 30 --22 --14 --6 TC2IRQ 29 --21 --13 --5 TC1IRQ 28 --20 --12 --4 TC0IRQ 27 --19 --11 --3 US1IRQ 26 --18 IRQ2 10 --2 US0IRQ 25 --17 IRQ1 9 --1 SWIRQ 24 --16 IRQ0 8 PIOIRQ 0 FIQ * IS1 - IS31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt. 45 AIC Interrupt Clear Command Register Register Name: Access Type: 31 --23 --15 --7 WDIRQ AIC_ICCR Write only 30 --22 --14 --6 TC2IRQ 29 --21 --13 --5 TC1IRQ 28 --20 --12 --4 TC0IRQ 27 --19 --11 --3 US1IRQ 26 --18 IRQ2 10 --2 US0IRQ 25 --17 IRQ1 9 --1 SWIRQ 24 --16 IRQ0 8 PIOIRQ 0 FIQ * Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. AIC Interrupt Set Command Register Register Name: Access Type: 31 --23 --15 --7 WDIRQ AIC_ISCR Write only 30 --22 --14 --6 TC2IRQ 29 --21 --13 --5 TC1IRQ 28 --20 --12 --4 TC0IRQ 27 --19 --11 --3 US1IRQ 26 --18 IRQ2 10 --2 US0IRQ 25 --17 IRQ1 9 --1 SWIRQ 24 --16 IRQ0 8 PIOIRQ 0 FIQ * Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 46 AT91M40400 AT91M40400 AIC End of Interrupt Command Register Register Name: Access Type: 31 --- AIC_EOICR Write only 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 --- 22 --- 21 --- 20 --- 19 --- 18 --- 17 --- 16 --- 15 --- 14 --- 13 --- 12 --- 11 --- 10 --- 9 --- 8 --- 7 --- 6 --- 5 --- 4 --- 3 --- 2 --- 1 --- 0 --- The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. AIC Spurious Vector Register Register Name: Access Type: Reset Value: 31 AIC_SPU Read/Write 0 30 29 28 SPUVEC 27 26 25 24 23 22 21 20 SPUVEC 19 18 17 16 15 14 13 12 SPUVEC 11 10 9 8 7 6 5 4 SPUVEC 3 2 1 0 * SPUVEC: Spurious Interrupt Vector Handler Address The user may store the address of the spurious interrupt handler in this register. 47 Standard Interrupt Sequence It is assumed that: * The Advanced Interrupt Controller has been programmed, AIC_SVR are loaded with corresponding interrupt service routine addresses and interrupts are enabled. * The Instruction at address 0x18(IRQ exception vector address) is ldr pc, [pc, #-&F20] When NIRQ is asserted, if the bit I of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the IRQ link register (r14_irq) and the Program Counter (r15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts r14_irq, decrementing it by 4. 2. The ARM core enters IRQ mode, if it is not already. 3. When the instruction loaded at address 0x18 is executed, the Program Counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: set the current interrupt to be the pending one with the highest priority. The current level is the priority level of the current interrupt. de-assert the NIRQ line on the processor. (Even if vectoring is not used, AIC_IVR must be read in order to de-assert NIRQ) automatically clear the interrupt, if it has been programmed to be edge triggered push the current level on to the stack return the value written in the AIC_SVR corresponding to the current interrupt 4. The previous step has effect to branch to the corresponding interrupt service routine. This should start by saving the Link Register(r14_irq) and the SPSR(SPSR_irq). Note that the Link Register must be decremented by 4 when it is saved, if it is to be restored directly into the Program Counter at the end of the interrupt. 5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allowing re-assertion of the NIRQ to be taken into account by the core. This can occur if an interrupt with a higher priority than the current one occurs. 6. The Interrupt Handler can then proceed as required, saving the registers which will be used and restoring them at the end. During this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. Note that if the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. The I bit in the CPSR must be set in order to mask interrupts before exiting, to ensure that the interrupt is completed in an orderly manner. 8. The End Of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than old current level but with higher priority than the new current level, the NIRQ line is re-asserted, but the interrupt sequence does not immediately start because the I bit is set in the core. 9. The SPSR (SPSR_irq) is restored. Finally, the saved value of the Link Register is restored directly into the PC. This has effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in the SPSR (the previous state of the ARM core). Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the mask instruction is completed (IRQ is masked). 48 AT91M40400 AT91M40400 Fast Interrupt Sequence It is assumed that: * The Advanced Interrupt Controller has been programmed, AIC_SVR[0] is loaded with fast interrupt service routine address and the fast interrupt is enabled. * The Instruction at address 0x1C(FIQ exception vector address) is: * ldr pc, [pc, #-&F20]. * Nested Fast Interrupts are not needed by the user. When NFIQ is asserted, if the bit F of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded in the FIQ link register (r14_fiq) and the Program Counter (r15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts r14_fiq, decrementing it by 4. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the Program Counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt (source 0 connected to the FIQ line), if it has been programmed to be edge triggered. In this case only, it de-asserts the NFIQ line on the processor. 4. The previous step has effect to branch to the corresponding interrupt service routine. It is not necessary to save the Link Register(r14_fiq) and the SPSR(SPSR_fiq) if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save registers r8 to r13 because FIQ mode has its own dedicated registers and the user r8 to r13 are banked. The other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the NFIQ line. 6. Finally, the Link Register (r14_fiq) is restored into the PC after decrementing it by 4 (with instruction sub pc, lr, #4 for example). This has effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the SPSR, masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). 49 PIO: Parallel I/O Controller The AT91M40400 has 32 programmable I/O lines. Six pins on the AT91M40400 are dedicated as general purpose I/O pins (P16, P17, P18, P19, P23 and P24). Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins (see Table 7). The PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller. Multiplexed I/O Lines Some I/O lines are multiplexed with an I/O signal of a peripheral. After reset, the pin is generally controlled by the PIO Controller and is in input mode. Table 7 indicates which of these pins are not controlled by the PIO Controller after reset. When a peripheral signal is not used in an application, the corresponding pin can be used as a parallel I/O. Each parallel I/O line is bi-directional, whether the peripheral defines the signal as input or output. Figure 33 shows the multiplexing of the peripheral signals with Parallel I/O signals. If a pin is multiplexed between the PIO Controller and a peripheral, the pin is controlled by the registers PIO_PER (PIO Enable) and PIO_PDR (PIO Disable). The register PIO_PSR (PIO Status) indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. If a pin is a general-purpose parallel I/O pin (not multiplexed with a peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the bits corresponding to these pins. When the PIO is selected, the peripheral input line is connected to zero. Output Selection The user can enable each individual I/O signal as an output wi th th e r eg is te r s P IO _O E R ( Ou tp ut E na bl e) a nd PIO_ODR (Output Disable). The output status of the I/O signals can be read in the register PIO_OSR (Output Status). The direction defined has effect only if the pin is configured to be controlled by the PIO Controller. I/O Levels Each pin can be configured to be driven high or low. The level is defined in four different ways, according to the following conditions. If a pin is controlled by the PIO Controller and is defined as an output (see Output Selection above), the level is programmed using the registers PIO_SODR (Set Output Data) and PIO_CODR (Clear Output Data). In this case, the programmed value can be read in PIO_ODSR (Output Data Status). If a pin is controlled by the PIO Controller and is not defined as an output, the level is determined by the external circuit. If a pin is not controlled by the PIO Controller, the state of the pin is defined by the peripheral (see peripheral datasheets). In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status). Filters Optional input glitch filtering is available on each pin and is controlled by the registers PIO_IFER (Input Filter Enable) and PIO_IFDR (Input Filter Disable). The input glitch filtering can be selected whether the pin is used for its peripheral function or as a parallel I/O line. The register PIO_IFSR (Input Filter Status) indicates whether or not the filter is activated for each pin. Interrupts Each parallel I/O can be programmed to generate an interrupt when a level change occurs. This is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Disable) registers which enable/disable the I/O interrupt by setting/clearing the corresponding bit in the PIO_IMR. When a change in level occurs, the corresponding bit in the PIO_ISR (Interrupt Status) is set whether the pin is used as a PIO or a peripheral and whether it is defined as input or output. If the corresponding interrupt in PIO_IMR (Interrupt Mask) is enabled, the PIO interrupt is asserted. When PIO_ISR is read, the register is automatically cleared. User Interface Each individual I/O is associated with a bit position in the Parallel I/O user interface registers. Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. 50 AT91M40400 AT91M40400 Figure 33. Parallel I/O Multiplexed with a Bi-directional Signal PIO_OSR Pad Output Enable 1 0 Peripheral Output Enable PIO_PSR PIO_ODSR Pad Output Pad 1 0 Peripheral Output Pad Input Filter 1 0 0 1 PIO_IFSR PIO_PSR Peripheral Input PIO_PDSR Event Detection PIO_ISR PIO_IMR PIOIRQ 51 Table 7. Multiplexed Parallel I/Os PIO Controller Bit Number(1) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Note: 1. Port Name P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 Port Name TCLK0 TIOA0 TIOB0 TCLK1 TIOA1 TIOB1 TCLK2 TIOA2 TIOB2 IRQ0 IRQ1 IRQ2 FIQ SCK0 TXD0 RXD0 - - - - SCK1 TXD1 RXD1 - - MCKO NCS2 NCS3 A20/CS7 A21/CS6 A22/CS5 A23/CS4 Peripheral Signal Description Timer 0 Clock signal Timer 0 Signal A Timer 0 Signal B Timer 1 Clock signal Timer 1 Signal A Timer 1 Signal B Timer 2 Clock signal Timer 2 Signal A Timer 2 Signal B External Interrupt 0 External Interrupt 1 External Interrupt 2 Fast Interrupt USART 0 clock signal USART 0 transmit data signal USART 0 receive data signal - - - - USART 1 clock signal USART 1 transmit data signal USART 1 receive data signal - - Master Clock Output Chip Select 2 Chip Select 3 Address 20/Chip Select 7 Address 21/Chip Select 6 Address 22/Chip Select 5 Address 23/Chip Select 4 Signal Direction input bi-directional bi-directional input bi-directional bi-directional input bi-directional bi-directional input input input input bi-directional output input - - - - bi-directional output input - - output output output output output output output Reset State PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input PIO Input MCKO NCS2 NCS3 A20 A21 A22 A23 Pin Number 49 50 51 54 55 56 57 58 59 60 63 64 66 67 68 69 70 71 72 73 74 75 76 83 84 85 99 100 25 26 29 30 Bit number refers to the data bit which corresponds to this signal in each of the User Interface registers. 52 AT91M40400 AT91M40400 PIO User Interface PIO Base Address:0xFFFF0000 Table 8. PIO Controller Memory Map Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C Notes: 1. 2. Register PIO Enable Register PIO Disable Register PIO Status Register Reserved Output Enable Register Output Disable Register Output Status Register Reserved Input Filter Enable Register Input Filter Disable Register Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register Pin Data Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Name PIO_PER PIO_PDR PIO_PSR - PIO_OER PIO_ODR PIO_OSR - PIO_IFER PIO_IFDR PIO_IFSR - PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR PIO_ISR Access Write only Write only Read only - Write only Write only Read only - Write only Write only Read only - Write only Write only Read only Read only Write only Write only Read only Read only Reset State - - 0x01FFFFFF (see also Table 7) - - - 0 - - - 0 - - - 0 (see Note 1) - - 0 (see Note 2) The reset value of this register depends on the level of the external pins at reset. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have occurred on any pins between the reset and the read. 53 PIO Enable Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_PER Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to enable individual pins to be controlled by the PIO Controller instead of the associated peripheral. When the PIO is enabled, the associated peripheral input (if any) is held at logic zero. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 0 = No effect. PIO Disable Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_PDR Write Only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral function is enabled on the corresponding pin. 1 = Disables PIO control (enables peripheral control) on the corresponding pin. 0 = No effect. 54 AT91M40400 AT91M40400 PIO Status Register Register Name: Access Type: Reset Value: 31 P31 23 P23 15 P15 7 P7 PIO_PSR Read only 0x01FFFFFF 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or disabled. 1 = PIO is active on the corresponding line (peripheral is inactive). 0 = PIO is inactive on the corresponding line (peripheral is active). 55 PIO Output Enable Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_OER Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to enable PIO output drivers. If the pin is driven by a peripheral, this has no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Enables the PIO output on the corresponding pin. 0 = No effect. PIO Output Disable Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_ODR Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to disable PIO output drivers. If the pin is driven by the peripheral, this has no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Disables the PIO output on the corresponding pin. 0 = No effect. 56 AT91M40400 AT91M40400 PIO Output Status Register Register Name: Access Type: Reset Value: 31 P31 23 P23 15 P15 7 P7 PIO_OSR Read only 0 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows: 1 = The corresponding PIO is output on this line. 0 = The corresponding PIO is input on this line. 57 PIO Input Filter Enable Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_IFER Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to enable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is programmed as follows: 1 = Enables the glitch filter on the corresponding pin. 0 = No effect. PIO Input Filter Disable Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 IO_IFDR Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to disable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is programmed as follows: 1 = Disables the glitch filter on the corresponding pin. 0 = No effect. 58 AT91M40400 AT91M40400 PIO Input Filter Status Register Register Name: Access Type: Reset Value: 31 P31 23 P23 15 P15 7 P7 PIO_IFSR Read only 0 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register indicates which pins have glitch filters selected. It is updated when PIO outputs are enabled or disabled by writing to PIO_IFER or PIO_IFDR. 1 = Filter is selected on the corresponding input (peripheral and PIO). 0 = Filter is not selected on the corresponding input. 59 PIO Set Output Data Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_SODR Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is set. 0 = No effect. PIO Clear Output Data Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_CODR Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is cleared. 0 = No effect. 60 AT91M40400 AT91M40400 PIO Output Data Status Register Register Name: Access Type: Reset Value: 31 P31 23 P23 15 P15 7 P7 PIO_ODSR Read only 0 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effective only if the pin is controlled by the PIO Controller and only if the pin is defined as an output. 1 = The output data for the corresponding line is programmed to 1. 0 = The output data for the corresponding line is programmed to 0. PIO Pin Data Status Register Register Name: Access Type: Reset Value: 31 P31 23 P23 15 P15 7 P7 PIO_PDSR Read only Undefined 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register shows the state of the physical pin of the chip. The pin values are always valid regardless of whether the pins are enabled as PIO, peripheral, input or output. The register reads as follows: 1 = The corresponding pin is at logic 1. 0 = The corresponding pin is at logic 0. 61 PIO Interrupt Enable Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_IER Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to enable PIO interrupts on the corresponding pin. It has effect whether PIO is enabled or not. 1 = Enables an interrupt when a change of logic level is detected on the corresponding pin. 0 = No effect. PIO Interrupt Disable Register Register Name: Access Type: 31 P31 23 P23 15 P15 7 P7 PIO_IDR Write only 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register is used to disable PIO interrupts on the corresponding pin. It has effect whether the PIO is enabled or not. 1 = Disables the interrupt on the corresponding pin. Logic level changes are still detected. 0 = No effect. 62 AT91M40400 AT91M40400 PIO Interrupt Mask Register Register Name: Access Type: Reset Value: 31 P31 23 P23 15 P15 7 P7 PIO_IMR Read Only 0 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR. 1 = Interrupt is enabled on the corresponding input pin. 0 = Interrupt is not enabled on the corresponding input pin. PIO Interrupt Status Register Register Name: Access Type: Reset Value: 31 P31 23 P23 15 P15 7 P7 PIO_ISR Read only 0 30 P30 22 P22 14 P14 6 P6 29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0 This register indicates for each pin when a logic value change has been detected (rising or falling edge). This is valid whether the PIO is selected for the pin or not and whether the pin is an input or output. The register is reset to zero following a read, and at reset. 1 = At least one change has been detected on the corresponding pin since the register was last read. 0 = No change has been detected on the corresponding pin since the register was last read. 63 USART: Universal Synchronous/Asynchronous Receiver/Transmitter The AT91M40400 provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: * Programmable Baud Rate Generator * Parity, Framing and Overrun Error Detection Figure 34. USART Block Diagram ASB Peripheral Data Controller AMBA Receiver Channel Transmitter Channel PIO: Parallel I/O Controller * * * * * * Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback channel modes Multi-drop Mode: Address Detection and Generation Interrupt Generation Two Dedicated Peripheral Data Controller channels 5-, 6-, 7- and 8-bit character length USART Channel APB Control Logic Receiver RXD USxIRQ Interrupt Control MCKI Baud Rate Generator MCKI/8 Baud Rate Clock Transmitter TXD SCK Pin Description Each USART channel has the following external signals: Name SCK TXD RXD Description USART Serial clock can be configured as input or output: SCK is configured as input if an External clock is selected (USCLKS[1] = 1) SCK is driven as output if the External Clock is disabled (USCLKS[1] = 0) and Clock output is enabled (CLKO = 1) Transmit Serial Data is an output Receive Serial Data is an input Note: After a hardware reset, the USART pins are not enabled by default (see PIO: Parallel I/O Controller on page 50). The user must configure the PIO Controller before enabling the transmitter or receiver. If the user selects one of the internal clocks, SCK can be configured as a PIO. 64 AT91M40400 AT91M40400 Baud Rate Generator The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the Receiver and the Transmitter. The Baud Rate Generator can select between external and internal clock sources. The external clock source is SCK. The internal clock sources can be either the master clock MCKI or the master clock divided by 8 (MCKI/8). Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (MCKI) period. The external clock frequency must be at least 2.5 times lower than the system clock. When the USART is programmed to operate in Asynchronous Mode (SYNC = 0 in the Mode Register US_MR), the selected clock is divided by 16 times the value (CD) written i n US _ B R G R ( B a u d R at e G e n e r a to r Re g i s t e r ) . I f US_BRGR is set to 0, the Baud Rate Clock is disabled. Baud Rate = Selected Clock 16 x CD When the USART is programmed to operate in Synchronous Mode (SYNC = 1) and the selected clock is internal (USCLKS[1] = 0 in the Mode Register US_MR), the Baud Rate Clock is the internal selected clock divided by the value written in US_BRGR. If US_BRGR is set to 0, the Baud Rate Clock is disabled. Baud Rate = Selected Clock CD In Synchronous Mode with external clock selected (USCLKS[1] = 1), the clock is provided directly by the signal on the SCK pin. No division is active. The value written in US_BRGR has no effect. Figure 35. Baud Rate Generator USCLKS [0] USCLKS [1] MCKI MCKI/8 SCK 0 1 0 CLK CD CD 16-Bit Counter OUT 1 >1 1 0 0 1 SYNC USCLKS [1] SYNC 0 Divide by 16 0 Baud Rate Clock 1 65 Receiver Asynchronous Receiver The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of US_MR). In asynchronous mode, the USART detects the start of a received character by sampling the RXD signal until it detects a valid start bit. A low level (space) on RXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence a space which is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. Figure 36. Asynchronous Mode: Start Bit Detection When a valid start bit has been detected, the receiver samples the RXD at the theoretical mid-point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (one bit period) so the sampling point is 8 cycles (0.5 bit periods) after the start of the bit. The first sampling point is therefore 24 cycles (1.5 bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1 bit period) after the previous one. 16 x Baud Rate Clock RXD Sampling True Start Detection D0 Figure 37. Asynchronous Mode: Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit periods 1 bit period RXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 66 AT91M40400 AT91M40400 Synchronous Receiver When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate clock. If a low level is detected, it is considered as a start. Data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit. See example in Figure 38. Figure 38. Synchronous Mode: Character Reception Example: 8-bit, parity enabled 1 stop SCK RXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Receiver Ready When a complete character is received, it is transferred to the US_RHR and the RXRDY status bit in US_CSR is set. If US_RHR has not been read since the last transfer, the OVRE status bit in US_CSR is set. Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in US_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in US_CSR is set. Framing Error If a character is received with a stop bit at low level and with at least one data bit at high level, a framing error is generated. This sets FRAME in US_CSR. Time-Out This function allows an idle condition on the RXD line to be detected. The maximum delay for which the USART should wait for a new character to arrive while the RXD line is inactive (high level) is programmed in US_RTOR (Receiver Time-out). When this register is set to 0, no time-out is detected. Otherwise, the receiver waits for a first character and then initializes a counter which is decremented at each bit period and reloaded at each byte reception. When the counter reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first character with the STTTO (Start Time-Out) bit in US_CR Calculation of time-out duration: Duration = Value x 4 x Bit period 67 Transmitter The transmitter has the same behavior in both synchronous and asynchronous operating modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of the serial clock. See example in Figure 39. The number of data bits is selected in the CHRL field in US_MR. The parity bit is set according to the PAR field in US_MR. The number of stop bits is selected in the NBSTOP field in US_MR. When a character is written to US_THR (Transmit Holding), it is transferred to the Shift Register as soon as it is empty. When the transfer occurs, the TXRDY bit in US_CSR is set until a new character is written to US_THR. If Transmit Shift Register and US_THR are both empty, the TXEMPTY bit in US_CSR is set. Time-Guard The Time-guard function allows the transmitter to insert an idle state on the TXD line between two characters. The duration of the idle state is programmed in US_TTGR (Transmitter Time-Guard). When this register is set to zero, no time-guard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in US_TTGR Idle state duration between two characters = Time-guard value x Bit period Multi-Drop Mode When the field PAR in US_MR equals 11X (binary value), the USART is configured to run in Multi-drop mode. In this case, the parity error bit PARE in US_CSR is set when data is detected with a parity bit set to identify an address byte. PARE is cleared with the Reset Status Bits Command (RSTSTA) in US_CR. If the parity bit is detected low, identifying a data byte, PARE is not set. The transmitter sends an address byte (parity bit set) when a Send Address Command (SENDA) is written to US_CR. In this case, the next byte written to US_THR will be transmitted as an address. After this any byte transmitted will have the parity bit cleared. Figure 39. Synchronous and Asynchronous Modes: Character Transmission Example: 8-bit, parity enabled 1 stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 68 AT91M40400 AT91M40400 Break A break condition is a low signal level which has a duration of at least one character (including start/stop bits and parity). Transmit Break The transmitter generates a break condition on the TXD line when STTBRK is set in US_CR (Control Register). In this case, the character present in the Transmit Shift Register is completed before the line is held low. To cancel a break condition on the TXD line, the STPBRK command in US_CR must be set. The USART completes a minimum break duration of one character length. The TXD line then returns to high level (idle state) for at least 12 bit periods to ensure that the end of break is correctly detected. Then the transmitter resumes normal operation. The BREAK is managed like a character: * The STTBRK and the STPBRK commands are performed only if the transmitter is ready (bit TXRDY = 1 in US_CSR) * The STTBRK command blocks the transmitter holding register (bit TXRDY is cleared in US_CSR) until the break has started * A break is started when the Shift Register is empty (any previous character is fully transmitted). TXEMPTY is cleared in US_CSR. The break blocks the transmitter shift register until it is completed (high level for at least 12 bit periods after the STPBRK command is requested) In order to avoid unpredictable states: * STTBRK and STPBRK commands must not be requested at the same time * Once an STTBRK command is requested, further STTBRK commands are ignored until the BREAK is ended (high level for at least 12 bit periods) * All STPBRK commands requested without a previous STTBRK command are ignored * A byte written into the Transmit Holding Register while a break is pending but not started (US_CSR.TXRDY = 0) is ignored * It is not permitted to write new data in the Transmit Holding Register while a break is in progress (STPBRK has not been requested), even though TXRDY = 1 in US_CSR. * A new STTBRK command must not be issues until an existing break has ended (TXEMPTY= 1 in US_CSR) The standard break transmission sequence is: 1. Wait for the transmitter ready (US_CSR.TXRDY = 1) 2. Send the STTBRK command (write 0x0200 to US_CR) 3. Wait for the transmitter ready (TXRDY = 1 in US_CSR) 4. Send the STPBRK command (write 0x0400 to US_CR) The next byte can then be sent: 5. Wait for the transmitter ready (TXRDY = 1 in US_CSR) 6. Send the next byte (write byte to US_THR) Each of these steps can be scheduled by using the interrupt if the bit TXRDY in US_IMR is set. For character transmission, the USART channel must be enabled before sending a break. Receive Break The receiver detects a break condition when all data, parity and stop bits are low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or at least one sample in synchronous operating mode. RXBRK is also asserted when an end of break is detected. Both the beginning and the end of a break can be detected by interrupt if the bit US_IMR.RXBRK is set. Peripheral Data Controller Each USART channel is closely connected to a corresponding Peripheral Data Controller channel. One is dedicated to the receiver. The other is dedicated to the transmitter. The PDC channel is programmed using US_TPR (Transmit Pointer) and US_TCR (Transmit Counter) for the transmitter and US_RPR (Receive Pointer) and US_RCR (Receive Counter) for the receiver. The status of the PDC is given in US_CSR by the ENDTX bit for the transmitter and by the ENDRX bit for the receiver. The pointer registers (US_TPR and US_RPR) are used to store the address of the transmit or receive buffers. The counter registers (US_TCR and US_RCR) are used to store the size of these buffers. The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is triggered by TXRDY. When a transfer is performed, the counter is decremented and the pointer is incremented. When the counter reaches 0, the status bit is set (ENDRX for the receiver, ENDTX for the transmitter in US_CSR) which can be programmed to generate an interrupt. Transfers are then disabled until a new non-zero counter value is programmed. 69 Interrupt Generation Each status bit in US_CSR has a corresponding bit in US_IER (Interrupt Enable) and US_IDR (Interrupt Disable) which controls the generation of interrupts by asserting the USART interrupt line connected to the Advanced Interrupt Controller. US_IMR (Interrupt Mask Register) indicates the status of the corresponding bits. When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is asserted. Figure 40. Channel Modes Automatic Echo Receiver RXD Transmitter Disabled TXD Channel Modes The USART can be programmed to operate in three different test modes, using the field CHMODE in US_MR. Automatic echo mode allows bit by bit re-transmission. When a bit is received on the RXD line, it is sent to the TXD line. Programming the transmitter has no effect. Local loopback mode allows the transmitted characters to be received. TXD and RXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The RXD pin level has no effect and the TXD pin is held high, as in idle state. Remote loopback mode directly connects the RXD pin to the TXD pin. The Transmitter and the Receiver are disabled and have no effect. This mode allows bit by bit retransmission. Local Loopback Receiver Disabled RXD VDD Transmitter Disabled TXD Remote Loopback Receiver VDD Disabled RXD Transmitter Disabled TXD 70 AT91M40400 AT91M40400 USART User Interface Base Address USART0: Base Address USART1: Table 9. USART Memory Map Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Time-guard Register Reserved Receive Pointer Register Receive Counter Register Transmit Pointer Register Transmit Counter Register Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR - US_RPR US_RCR US_TPR US_TCR Access Write only Read/Write Write only Write only Read only Read only Read only Write only Read/Write Read/Write Read/Write - Read/Write Read/Write Read/Write Read/Write Reset State - 0 - - 0 0x18 0 - 0 0 0 - 0 0 0 0 0xFFFD0000 0xFFFCC000 71 USART Control Register Name: Access Type: 31 --23 --15 --7 TXDIS US_CR Write only 30 --22 --14 --6 TXEN 29 --21 --13 --5 RXDIS 28 --20 --12 SENDA 4 RXEN 27 --19 --11 STTTO 3 RSTTX 26 --18 --10 STPBRK 2 RSTRX 25 --17 --9 STTBRK 1 --24 --16 --8 RSTSTA 0 --- * * * * * * * * * * * RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset. RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset. RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR. STTBRK: Start Break 0 = No effect. 1 = If break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. STPBRK: Stop Break 0 = No effect. 1 = If a break is being transmitted, stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. STTTO: Start Time-out 0 = No effect. 1 = Start waiting for a character before clocking the time-out counter. SENDA: Send Address 0 = No effect. 1 = In Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set. 72 AT91M40400 AT91M40400 USART Mode Register Name: Access Type: 31 --23 --15 CHMODE 7 CHRL 6 5 USCLKS US_MR Read/Write 30 --22 --14 29 --21 --13 NBSTOP 4 3 --28 --20 --12 27 --19 --11 26 --18 CLKO 10 PAR 2 --1 --25 --17 --9 24 --16 --8 SYNC 0 --- * USCLKS: Clock Selection (Baud Rate Generator Input Clock) USCLKS 0 0 1 0 1 X Selected Clock MCKI MCKI/8 External (SCK) * CHRL: Character Length CHRL 0 0 1 1 0 1 0 1 Character Length Five bits Six bits Seven bits Eight bits * * Start, stop and parity bits are added to the character length. SYNC: Synchronous Mode Select 0 = USART operates in Asynchronous Mode. 1 = USART operates in Synchronous Mode. PAR: Parity Type PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even Parity Odd Parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multi-drop mode 73 * NBSTOP: Number of Stop Bits The interpretation of the number of stop bits depends on SYNC. NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved * CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode The USART Channel operates as an Rx/Tx USART. Automatic Echo Receiver Data Input is connected to the TXD pin. Local Loopback Transmitter Output Signal is connected to Receiver Input Signal. Remote Loopback RXD pin is internally connected to TXD pin. * CKLO: Clock Output Select 0 = The USART does not drive the SCK pin. 1 = The USART drives the SCK pin if USCLKS[1] is 0. 74 AT91M40400 AT91M40400 USART Interrupt Enable Register Name: Access Type: 31 --23 --15 --7 PARE US_IER Write only 30 --22 --14 --6 FRAME 29 --21 --13 --5 OVRE 28 --20 --12 --4 ENDTX 27 --19 --11 --3 ENDRX 26 --18 --10 --2 RXBRK 25 --17 --9 TXEMPTY 1 TXRDY 24 --16 --8 TIMEOUT 0 RXRDY * * * * * * * * * * RXRDY: Enable RXRDY Interrupt 0 = No effect. 1 = Enables RXRDY Interrupt. TXRDY: Enable TXRDY Interrupt 0 = No effect. 1 = Enables TXRDY Interrupt. RXBRK: Enable Receiver Break Interrupt 0 = No effect. 1 = Enables Receiver Break Interrupt. ENDRX: Enable End of Receive Transfer Interrupt 0 = No effect. 1 = Enables End of Receive Transfer Interrupt. ENDTX: Enable End of Transmit Interrupt 0 = No effect. 1 = Enables End of Transmit Interrupt. OVRE: Enable Overrun Error Interrupt 0 = No effect. 1 = Enables Overrun Error Interrupt. FRAME: Enable Framing Error Interrupt 0 = No effect. 1 = Enables Framing Error Interrupt. PARE: Enable Parity Error Interrupt 0 = No effect. 1 = Enables Parity Error Interrupt. TIMEOUT: Enable Time-out Interrupt 0 = No effect. 1 = Enables Reception Time-out Interrupt. TXEMPTY: Enable TXEMPTY Interrupt 0 = No effect. 1 = Enables TXEMPTY Interrupt. 75 USART Interrupt Disable Register Name: Access Type: 31 --23 --15 --7 PARE US_IDR Write only 30 --22 --14 --6 FRAME 29 --21 --13 --5 OVRE 28 --20 --12 --4 ENDTX 27 --19 --11 --3 ENDRX 26 --18 --10 --2 RXBRK 25 --17 --9 TXEMPTY 1 TXRDY 24 --16 --8 TIMEOUT 0 RXRDY * * * * * * * * * * RXRDY: Disable RXRDY Interrupt 0 = No effect. 1 = Disables RXRDY Interrupt. TXRDY: Disable TXRDY Interrupt 0 = No effect. 1 = Disables TXRDY Interrupt. RXBRK: Disable Receiver Break Interrupt 0 = No effect. 1 = Disables Receiver Break Interrupt. ENDRX: Disable End of Receive Transfer Interrupt 0 = No effect. 1 = Disables End of Receive Transfer Interrupt. ENDTX: Disable End of Transmit Interrupt 0 = No effect. 1 = Disables End of Transmit Interrupt. OVRE: Disable Overrun Error Interrupt 0 = No effect. 1 = Disables Overrun Error Interrupt. FRAME: Disable Framing Error Interrupt 0 = No effect. 1 = Disables Framing Error Interrupt. PARE: Disable Parity Error Interrupt 0 = No effect. 1 = Disables Parity Error Interrupt. TIMEOUT: Disable Time-out Interrupt 0 = No effect. 1 = Disables Receiver Time-out Interrupt. TXEMPTY: Disable TXEMPTY Interrupt 0 = No effect. 1 = Disables TXEMPTY Interrupt. 76 AT91M40400 AT91M40400 USART Interrupt Mask Register Name: Access Type: 31 --23 --15 --7 PARE US_IMR Read only 30 --22 --14 --6 FRAME 29 --21 --13 --5 OVRE 28 --20 --12 --4 ENDTX 27 --19 --11 --3 ENDRX 26 --18 --10 --2 RXBRK 25 --17 --9 TXEMPTY 1 TXRDY 24 --16 --8 TIMEOUT 0 RXRDY * * * * * * * * * * RXRDY: Mask RXRDY Interrupt 0 = RXRDY Interrupt is Disabled 1 = RXRDY Interrupt is Enabled TXRDY: Mask TXRDY Interrupt 0 = TXRDY Interrupt is Disabled 1 = TXRDY Interrupt is Enabled RXBRK: Mask Receiver Break Interrupt 0 = Receiver Break Interrupt is Disabled 1 = Receiver Break Interrupt is Enabled ENDRX: Mask End of Receive Transfer Interrupt 0 = End of Receive Transfer Interrupt is Disabled 1 = End of Receive Transfer Interrupt is Enabled ENDTX: Mask End of Transmit Interrupt 0 = End of Transmit Interrupt is Disabled 1 = End of Transmit Interrupt is Enabled OVRE: Mask Overrun Error Interrupt 0 = Overrun Error Interrupt is Disabled 1 = Overrun Error Interrupt is Enabled FRAME: Mask Framing Error Interrupt 0 = Framing Error Interrupt is Disabled 1 = Framing Error Interrupt is Enabled PARE: Mask Parity Error Interrupt 0 = Parity Error Interrupt is Disabled 1 = Parity Error Interrupt is Enabled TIMEOUT: Mask Time-out Interrupt 0 = Receive Time-out Interrupt is Disabled 1 = Receive Time-out Interrupt is Enabled TXEMPTY: Mask TXEMPTY Interrupt 0 = TXEMPTY Interrupt is Disabled. 1 = TXEMPTY Interrupt is Enabled. 77 USART Channel Status Register Name: Access Type: 31 --23 --15 --7 PARE US_CSR Read only 30 --22 --14 --6 FRAME 29 --21 --13 --5 OVRE 28 --20 --12 --4 ENDTX 27 --19 --11 --3 ENDRX 26 --18 --10 --2 RXBRK 25 --17 --9 TXEMPTY 1 TXRDY 24 --16 --8 TIMEOUT 0 RXRDY * * * * * * * * * * RXRDY: Receiver Ready 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. 1 = At least one complete character has been received and the US_RHR has not yet been read. TXRDY: Transmitter Ready 0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested. 1 = US_THR is empty and there is no Break request pending TSR availability. Equal to zero when the USART is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one. RXBRK: Break Received/End of Break 0 = No Break Received nor End of Break has been detected since the last "Reset Status Bits" command in the Control Register. 1 = Break Received or End of Break has been detected since the last "Reset Status Bits" command in the Control Register. ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. OVRE: Overrun Error 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last "Reset Status Bits" command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last "Reset Status Bits" command. FRAME: Framing Error 0 = No stop bit has been detected low since the last "Reset Status Bits" command. 1 = At least one stop bit has been detected low since the last "Reset Status Bits" command. PARE: Parity Error 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last "Reset Status Bits" command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last "Reset Status Bits" command. TIMEOUT: Receiver Time-out 0 = There has not been a time-out since the last "Start Time-out" command or the Time-out Register is 0. 1 = There has been a time-out since the last "Start Time-out" command. TXEMPTY: Transmitter Empty 0 = There are characters in either US_THR or the Transmit Shift Register or a Break is being transmitted. 1 = There are no characters in US_THR and the Transmit Shift Register and Break is not active. Equal to zero when the USART is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one. 78 AT91M40400 AT91M40400 USART Receiver Holding Register Name: Access Type: 31 --23 --15 --7 US_RHR Read only 30 --22 --14 --6 29 --21 --13 --5 28 --20 --12 --4 RXCHR 27 --19 --11 --3 26 --18 --10 --2 25 --17 --9 --1 24 --16 --8 --0 * RXCHR: Received Character Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-significant bits read zero. USART Transmitter Holding Register Name: Access Type: 31 --23 --15 --7 US_THR Write only 30 --22 --14 --6 29 --21 --13 --5 28 --20 --12 --4 TXCHR 27 --19 --11 --3 26 --18 --10 --2 25 --17 --9 --1 24 --16 --8 --0 * TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned. 79 USART Baud Rate Generator Register Name: Access Type: 31 --23 --15 US_BRGR Read/Write 30 --22 --14 29 --21 --13 28 --20 --12 CD 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 5 4 CD 3 2 1 0 * CD: Clock Divisor This register has no effect if Synchronous Mode is selected with an external clock. CD 0 1 2 to 65535 Disables Clock Clock Divisor bypass Baud Rate (Asynchronous Mode) = Selected clock / (16 x CD) Baud Rate (Synchronous Mode) = Selected clock / CD Note: In Synchronous Mode, the value programmed must be even to ensure a 50:50 mark:space ratio. Note: Clock divisor bypass (CD = 1) must not be used when internal clock MCKI is selected (USCLKS = 0). 80 AT91M40400 AT91M40400 USART Receiver Time-out Register Name: Access Type: 31 --23 --15 --7 US_RTOR Read/Write 30 --22 --14 --6 29 --21 --13 --5 28 --20 --12 --4 TO 27 --19 --11 --3 26 --18 --10 --2 25 --17 --9 --1 24 --16 --8 --0 * TO: Time-out Value When a value is written to this register, a Start Time-out Command is automatically performed. TO 0 1-255 Disables the RX Time-out function. The Time-out counter is loaded with TO when the Start Time-out Command is given or when each new data character is received (after reception has started). Time-out duration = TO x 4 x Bit period USART Transmitter Time-guard Register Name: Access Type: 31 --23 --15 --7 US_TTGR Read/Write 30 --22 --14 --6 29 --21 --13 --5 28 --20 --12 --4 TG 27 --19 --11 --3 26 --18 --10 --2 25 --17 --9 --1 24 --16 --8 --0 * TG: Time-guard Value TG 0 1-255 Disables the TX Time-guard function. TXD is inactive high after the transmission of each character for the time-guard duration. Time-guard duration = TG x Bit period 81 USART Receive Pointer Register Name: Access Type: 31 US_RPR Read/Write 30 29 28 RXPTR 27 26 25 24 23 22 21 20 RXPTR 19 18 17 16 15 14 13 12 RXPTR 11 10 9 8 7 6 5 4 RXPTR 3 2 1 0 * RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. USART Receive Counter Register Name: Access Type: 31 --23 --15 US_RCR Read/Write 30 --22 --14 29 --21 --13 28 --4920 --12 RXCTR 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 5 4 RXCTR 3 2 1 0 * RXCTR: Receive Counter RXCTR must be loaded with the size of the receive buffer. 0: Stop Peripheral Data Transfer dedicated to the receiver. 1-65535: Start Peripheral Data transfer if RXRDY is active. 82 AT91M40400 AT91M40400 USART Transmit Pointer Register Name: Access Type: 31 US_TPR Read/Write 30 29 28 TXPTR 27 26 25 24 23 22 21 20 TXPTR 19 18 17 16 15 14 13 12 TXPTR 11 10 9 8 7 6 5 4 TXPTR 3 2 1 0 * TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. USART Transmit Counter Register Name: Access Type: 31 --23 --15 US_TCR Read/Write 30 --22 --14 29 --21 --13 28 --20 --12 TXCTR 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 5 4 TXCTR 3 2 1 0 * TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0: Stop Peripheral Data Transfer dedicated to the transmitter. 1-65535: Start Peripheral Data transfer if TXRDY is active. 83 TC: Timer Counter The AT91M40400 features a Timer Counter block which includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each Timer Counter channel has 3 external clock inputs, 5 internal clock inputs, and 2 multi-purpose input/output signals which can be configured by the user. Each channel Figure 41. TC Block Diagram drives an internal interrupt signal which can be programmed to generate processor interrupts via the AIC (Advanced Interrupt Controller). The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each Timer Counter channel, allowing them to be chained. MCKI/2 Parallel IO Controller TCLK0 TIOA1 TIOA2 XC0 XC1 XC2 TC0XC0S SYNC MCKI/8 MCKI/32 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TCLK1 MCKI/128 MCKI/1024 Timer Counter Channel 0 TIOA TIOA0 TIOB TCLK2 TIOB0 INT TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC Timer Counter Channel 1 TIOA TIOA1 TIOB TIOB1 INT TIOA1 TIOB1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer Counter Channel 2 TIOA TIOA2 TIOB TIOB2 SYNC TIOA2 TIOB2 INT Timer Counter Block Advanced Interrupt Controller 84 AT91M40400 AT91M40400 Signal Name Description Channel Signal XC0, XC1, XC2 TIOA TIOB INT SYNC Block Signals TCLK0, TCLK1, TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 Description External Clock Inputs Capture Mode: General purpose input Waveform Mode: General purpose output Capture Mode: General purpose input Waveform Mode: General purpose input/output Interrupt signal output Synchronization input signal Description External Clock Inputs TIOA signal for Channel 0 TIOB signal for Channel 0 TIOA signal for Channel 1 TIOB signal for Channel 1 TIOA signal for Channel 2 TIOB signal for Channel 2 Note: After a hardware reset, the Timer Counter block pins are controlled by the PIO Controller. They must be configured to be controlled by the peripheral before being used. Timer Counter Description The three Timer Counter channels are independent and identical in operation. The registers for channel programming are listed in Table 11. Counter Each Timer Counter channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the bit COVFS in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). Each channel can independently select an internal or external clock source for its counter: * Internal clock signals: MCKI/2, MCKI/8, MCKI/32, MCKI/128, MCKI/1024 * External clock signals: XC0, XC1 or XC2 The selected clock can be inverted with the CLKI bit in TC_CMR (Channel Mode). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (MCKI) period. The external clock frequency must be at least 2.5 times lower than the system clock (MCKI). Figure 42. Clock Selection CLKS CLKI MCKI/2 MCKI/8 MCKI/32 MCKI/128 MCKI/1024 XC0 XC1 XC2 Selected Clock BURST 1 85 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. * The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. * The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. Figure 43. Clock Control Selected Clock Trigger Timer Counter Operating Modes Each Timer Counter channel can independently operate in two different modes: * Capture Mode allows measurement on signals * Waveform Mode allows wave generation The Timer Counter Operating Mode is programmed with the WAVE bit in the TC Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: * Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. * SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. * Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The Timer Counter channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the system clock (MCKI) period in order to be detected. Whatever the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value may not read zero just after a trigger, especially when a low frequency signal is selected as the clock. CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 86 AT91M40400 AT91M40400 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC Channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are inputs. Figure 44 shows the configuration of the TC Channel when programmed in Capture Mode. Capture Registers A and B (RA and RB) Registers A and B are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The parameter LDRA in TC_CMR defines the TIOA edge for the loading of register A, and the parameter LDRB defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger. Parameter ETRGEDG defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. Status Register The following bits in the status register are significant in Capture Operating Mode. * CPCS: RC Compare Status There has been an RC Compare match at least once since the last read of the status * COVFS: Counter Overflow Status The counter has attempted to count past $FFFF since the last read of the status * LOVRS: Load Overrun Status RA or RB has been loaded at least twice without any read of the corresponding register, since the last read of the status * LDRAS: Load RA Status RA has been loaded at least once without any read, since the last read of the status * LDRBS: Load RB Status RB has been loaded at least once without any read, since the last read of the status * ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status 87 Figure 44. Capture Mode 88 AT91M40400 TCCLKS CLKI MCKI/2 MCKI/8 MCKI/32 MCKI/128 MCKI/1024 XC0 XC1 XC2 LDBSTOP BURST Register C Capture Register A SWTRG 16-bit Counter CLK OVF RESET CLKSTA CLKEN CLKDIS Q Q S R S R LDBDIS 1 Capture Register B Compare RC = SYNC ABETRG ETRGEDG MTIOB Edge Detector LDRA Edge Detector Trig CPCTRG TIOB LDRB Edge Detector If RA is loaded ETRGS COVFS LOVRS LDRAS LDRBS TC_SR CPCS MTIOA If RA is not loaded or RB is loaded TIOA TC_IMR Timer Counter Channel INT AT91M40400 Waveform Operating Mode This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). Waveform Operating Mode allows the TC Channel to generate 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or to generate different types of one-shot or repetitive pulses. In this mode, TIOA is configured as output and TIOB is defined as output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 45 shows the configuration of the TC Channel when programmed in Waveform Operating Mode. Compare Register A, B and C (RA, RB, and RC) In Waveform Operating Mode, RA, RB and RC are all used as compare registers. RA Compare is used to control the TIOA output. RB Compare is used to control the TIOB (if configured as output). RC Compare can be programmed to control TIOA and/or TIOB outputs. RC Compare can also stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). As in Capture Mode, RC Compare can also generate a trigger if CPCTRG = 1. A trigger resets the counter so RC can control the period of PWM waveforms. External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The parameter EEVT in TC_CMR selects the external trigger. The parameter EEVTEDG defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as output and the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal, the software trigger and the RC compare trigger are also available as triggers. Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. The tables below show which parameter in TC_CMR is used to define the effect of each event. Parameter ASWTRG AEEVT ACPC ACPA Parameter BSWTRG BEEVT BCPC BCPB TIOA Event Software trigger External event RC compare RA compare TIOB Event Software trigger External event RC compare RB compare If two or more events occur at the same time, the priority level is defined as follows: 1. Software trigger 2. External event 3. RC compare 4. RA or RB compare Status The following bits in the status register are significant in Waveform Mode: * CPAS: RA Compare Status there has been a RA Compare match at least once since the last read of the status * CPBS: RB Compare Status there has been a RB Compare match at least once since the last read of the status * CPCS: RC Compare Status there has been a RC Compare match at least once since the last read of the status * COVFS: Counter Overflow Counter has attempted to count past $FFFF since the last read of the status * ETRGS: External Trigger External trigger has been detected since the last read of the status 89 Figure 45. Waveform Mode MCKI/1024 XC0 XC1 XC2 Q S R Output Controller CPCTRG EEVT BEEVT EEVTEDG Edge Detector TIOB ENETRG ETRGS COVFS TC_SR CPCS CPAS CPBS Output Controller 90 TCCLKS AT91M40400 CLKSTA MCKI/2 MCKI/8 MCKI/32 MCKI/128 CLKI CLKEN CLKDIS ACPC Q S CPCDIS R ACPA MTIOA TIOA CPCSTOP AEEVT BURST Register A Register B Register C ASWTRG 1 16-bit Counter CLK RESET OVF Compare RA = Compare RB = Compare RC = SWTRG BCPC SYNC Trig BCPB MTIOB TIOB BSWTRG TC_IMR Timer Counter Channel INT AT91M40400 TC User Interface TC Base Address: 0xFFFE0000 Table 10. TC Global Memory Map Offset 0x00 0x40 0x80 0xC0 0xC4 Channel/Register TC Channel 0 TC Channel 1 TC Channel 2 TC Block Control Register TC Block Mode Register TC_BCR TC_BMR Name Access See Table 11 See Table 11 See Table 11 Write only Read/Write --0 Reset State TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC Channels are controlled by the registers listed in Table 11. The offset of each of the Channel registers in Table 11 is in relation to the offset of the corresponding channel as mentioned in Table 10. Table 11. TC Channel Memory Map Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C Note: 1. Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Read only if WAVE = 0 TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR Read/Write Read/Write(1) Read/Write(1) Read/Write Read only Write only Write only Read only Name TC_CCR TC_CMR Access Write only Read/Write Reset State --0 ----0 0 0 0 ------0 91 TC Block Control Register Register Name: Access Type: 31 --23 --15 --7 --- TC_BCR Write only 30 --22 --14 --6 --29 --21 --13 --5 --28 --20 --12 --4 --27 --19 --11 --3 --26 --18 --10 --2 --25 --17 --9 --1 --24 --16 --8 --0 SYNC * SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 92 AT91M40400 AT91M40400 TC Block Mode Register Register Name: Access Type: 31 --23 --15 --7 --- TC_BMR Read/Write 30 --22 --14 --6 --29 --21 --13 --5 TC2XC2S 28 --20 --12 --4 27 --19 --11 --3 TC1XC1S 26 --18 --10 --2 25 --17 --9 --1 TC0XC0S 24 --16 --8 --0 * TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 * TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 * TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 93 TC Channel Control Register Register Name: Access Type: 31 --23 --15 --7 --- TC_CCR Write only 30 --22 --14 --6 --29 --21 --13 --5 --28 --20 --12 --4 --27 --19 --11 --3 --26 --18 --10 --2 SWTRG 25 --17 --9 --1 CLKDIS 24 --16 --8 --0 CLKEN * * * CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and clock is started. 94 AT91M40400 AT91M40400 TC Channel Mode Register: Capture Mode Register Name: Access Type: 31 --23 --15 WAVE=0 7 LDBDIS TC_CMR Read/Write 30 --22 --14 CPCTRG 6 LDBSTOP 29 --21 --13 --5 BURST 28 --20 --12 --4 11 --3 CLKI 27 --19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 --18 25 --17 LDRA 8 24 --16 * TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected MCKI/2 MCKI/8 MCKI/32 MCKI/128 MCKI/1024 XC0 XC1 XC2 * * CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. * * LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. 95 * ETRGEDG: External Trigger Edge Selection ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge * * * * ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. WAVE = 0 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). LDRA: RA Loading Selection LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA * LDRB: RB Loading Selection LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA 96 AT91M40400 AT91M40400 TC Channel Mode Register: Waveform Mode Register Name: Access Type: 31 BSWTRG 23 ASWTRG 15 WAVE=1 7 CPCDIS 14 CPCTRG 6 CPCSTOP 13 --5 BURST 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS TC_CMR Read/Write 30 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24 * TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected MCKI/2 MCKI/8 MCKI/32 MCKI/128 MCKI/1024 XC0 XC1 XC2 * * CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. * * CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. 97 * EEVTEDG: External Event Edge Selection EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge * EEVT: External Event Selection EEVT 0 0 1 1 0 1 0 1 1. Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input(1) output output output Note: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. * * * * ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. WAVE = 1 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. ACPA: RA Compare Effect on TIOA ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle * ACPC: RC Compare Effect on TIOA ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle * AEEVT: External Event Effect on TIOA AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle 98 AT91M40400 AT91M40400 * ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle * BCPB: RB Compare Effect on TIOB BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle * BCPC: RC Compare Effect on TIOB BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle * BEEVT: External Event Effect on TIOB BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle * BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle 99 TC Counter Value Register Register Name: Access Type: 31 --23 --15 TC_CVR Read only 30 --22 --14 29 --21 --13 28 --20 --12 CV 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 5 4 CV 3 2 1 0 * CV: Counter Value CV contains the counter value in real time. TC Register A Register Name: Access Type: 31 --23 --15 TC_RA Read only if WAVE = 0, Read/Write if WAVE = 1 30 --22 --14 29 --21 --13 28 --20 --12 RA 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 5 4 RA 3 2 1 0 * RA: Register A RA contains the Register A value in real time. 100 AT91M40400 AT91M40400 TC Register B Register Name: Access Type: 31 --23 --15 TC_RB Read only if WAVE = 0, Read/Write if WAVE = 1 30 --22 --14 29 --21 --13 28 --20 --12 RB 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 5 4 RB 3 2 1 0 * RB: Register B RB contains the Register B value in real time. TC Register C Register Name: Access Type: 31 --23 --15 TC_RC Read/Write 30 --22 --14 29 --21 --13 28 --20 --12 RC 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 5 4 RC 3 2 1 0 * RC: Register C RC contains the Register C value in real time. 101 TC Status Register Register Name: Access Type: 31 --23 --15 --7 ETRGS TC_SR Read/Write 30 --22 --14 --6 LDRBS 29 --21 --13 --5 LDRAS 28 --20 --12 --4 CPCS 27 --19 --11 --3 CPBS 26 --18 MTIOB 10 --2 CPAS 25 --17 MTIOA 9 --1 LOVRS 24 --16 CLKSTA 8 --0 COVFS * * * * * * * * * * * COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 102 AT91M40400 AT91M40400 TC Interrupt Enable Register Register Name: Access Type: 31 --23 --15 --7 ETRGS TC_IER Write only 30 --22 --14 --6 LDRBS 29 --21 --13 --5 LDRAS 28 --20 --12 --4 CPCS 27 --19 --11 --3 CPBS 26 --18 --10 --2 CPAS 25 --17 --9 --1 LOVRS 24 --16 --8 --0 COVFS * * * * * * * * COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. LOVRS: Load Overrun 0 = No effect. 1: Enables the Load Overrun Interrupt. CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 103 TC Interrupt Disable Register Register Name: Access Type: 31 --23 --15 --7 ETRGS TC_IDR Write only 30 --22 --14 --6 LDRBS 29 --21 --13 --5 LDRAS 28 --20 --12 --4 CPCS 27 --19 --11 --3 CPBS 26 --18 --10 --2 CPAS 25 --17 --9 --1 LOVRS 24 --16 --8 --0 COVFS * * * * * * * * COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. 104 AT91M40400 AT91M40400 TC Interrupt Mask Register Register Name: Access Type: 31 --23 --15 --7 ETRGS TC_IMR Read only 30 --22 --14 --6 LDRBS 29 --21 --13 --5 LDRAS 28 --20 --12 --4 CPCS 27 --19 --11 --3 CPBS 26 --18 --10 --2 CPAS 25 --17 --9 --1 LOVRS 24 --16 --8 --0 COVFS * * * * * * * * COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 105 WD: Watchdog Timer The AT91M40400 has an internal watchdog timer which can be used to prevent system lock-up if the software becomes trapped in a deadlock. In normal operation the user reloads the watchdog at regular intervals before the timer overflow occurs. If an overflow does occur, the watchdog timer generates one or a combination of the following signals, depending on the parameters in WD_OMR (Overflow Mode Register): * If RSTEN is set, an internal reset is generated (WD_RESET as shown in Figure 46). See also Watchdog Reset on page 8. * If IRQEN is set, a pulse is generated on the signal WDIRQ which is connected to the Advanced Interrupt Controller * If EXTEN is set, a low level is driven on the NWDOVF signal for a duration of 8 MCKI cycles. Figure 46. Watchdog Timer Block Diagram The watchdog timer has a 16-bit down counter. Bits 12-15 of the value loaded when the watchdog is restarted are programmable using the HPVC parameter in WD_CMR (Clock Mode). Four clock sources are available to the watchdog counter: MCKI/8, MCKI/32, MCKI/128 or MCKI/1024. The selection is made using the WDCLKS parameter in WD_CMR. This provides a programmable time-out period of 1ms to 2s with a 33 MHz system clock. All write accesses are protected by control access keys to help prevent corruption of the watchdog should an error condition occur. To update the contents of the mode and control registers it is necessary to write the correct bit pattern to the control access key bits at the same time as the control bits are written (the same write access). Advanced Peripheral Bus (APB) WD_RESET WDIRQ Control Logic Overflow NWDOVF MCKI/8 MCKI/32 Clock Select MCKI/128 MCKI/1024 CLK_CNT Clear 16-Bit Programmable Down Counter WD User Interface WD Base Address: 0xFFFF8000 Table 12. WD Memory Map Offset 0x00 0x04 0x08 0x0C Register Overflow Mode Register Clock Mode Register Control Register Status Register Name WD_OMR WD_CMR WD_CR WD_SR Access Read/Write Read/Write Write only Read only Reset State 0 0 --0 106 AT91M40400 AT91M40400 WD Overflow Mode Register Name: Access: Reset Value: 31 --23 --15 WD_OMR Read/Write 0 30 --22 --14 29 --21 --13 28 --20 --12 OKEY 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 OKEY 5 4 3 EXTEN 2 IRQEN 1 RSTEN 0 WDEN * * * * * WDEN: Watch Dog Enable 0 = Watch Dog is disabled and does not generate any signals. 1 = Watch Dog is enabled and generates enabled signals. RSTEN: Reset Enable 0 = Generation of an internal reset by the Watch Dog is disabled. 1 = When overflow occurs, the Watch Dog generates an internal reset. IRQEN: Interrupt Enable 0 = Generation of an interrupt by the Watch Dog is disabled. 1 = When overflow occurs, the Watch Dog generates an interrupt. EXTEN: External Signal Enable 0 = Generation of a pulse on the pin NWDOVF by the Watch Dog is disabled. 1 = When an overflow occurs, a pulse on the pin NWDOVF is generated. OKEY: Overflow Access Key Used only when writing WD_OMR. OKEY is read as 0. 0x234 = Write access in WD_OMR is allowed. Other value = Write access in WD_OMR is prohibited. 107 WD Clock Mode Register Name: Access: Reset Value: 31 --23 --15 WD_CMR Read/Write 0 30 --22 --14 29 --21 --13 28 --20 --12 CKEY 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 CKEY 6 --- 5 4 HPCV 3 2 1 WDCLKS 0 * WDCLKS: Clock Selection WDCLKS 0 0 1 1 0 1 0 1 Clock Selected MCKI/8 MCKI/32 MCKI/128 MCKI/1024 * * HPCV: High Preload Counter Value Counter is preloaded when watchdog counter is restarted with bits 0 to 11 set (FFF) and bits 12 to 15 equaling HPCV. CKEY: Clock Access Key Used only when writing WD_CMR. CKEY is read as 0. 0x06E: Write access in WD_CMR is allowed. Other value: Write access in WD_CMR is prohibited. 108 AT91M40400 AT91M40400 WD Control Register Name: Access: 31 --23 --15 WD_CR Write only 30 --22 --14 29 --21 --13 28 --20 --12 RSTKEY 27 --19 --11 26 --18 --10 25 --17 --9 24 --16 --8 7 6 5 4 RSTKEY 3 2 1 0 * RSTKEY: Restart Key 0xC071 = Watch Dog counter is restarted. Other value = No effect. WD Status Register Name: Access: 31 -23 -15 -7 -- WD_SR Read only 30 -22 -14 -6 -29 -21 -13 -5 -28 -20 -12 -4 -27 -19 -11 -3 -26 -18 -10 -2 -25 -17 -9 -1 -24 -16 -8 -0 WDOVF * WDOVF: Watchdog Overflow 0 = No watchdog overflow. 1 = A watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset. 109 WD Enabling Sequence To enable the Watchdog Timer the sequence is as follows: 1. Disable the Watchdog by clearing the bit WDEN: Write 0x2340 to WD_OMR This step is unnecessary if the WD is already disabled (reset state). 2. Initialize the WD Clock Mode Register: Write 0x373C to WD_CMR (HPCV = 15 and WDCLKS = MCK/8) 3. Restart the timer: Write 0xC071 to WD_CR 4. Enable the watchdog: Write 0x2345 to WD_OMR (interrupt enabled) 110 AT91M40400 AT91M40400 PS: Power Saving The AT91M40400 Power Saving module provides a lowpower Idle Mode. In Idle Mode, the CPU clock is deactivated while all on-chip peripherals and the RAM remain active. The contents of the on-chip RAM and all the special function registers remain unchanged during this mode. The Idle Mode can be terminated by any enabled interrupt or by a hardware Reset. PS User Interface Base Address: 0xFFFF4000 Table 13. Power Saving Memory Map Offset 0x00 Register Control Register Name PS_CR Access Write only Reset State 0 PS Control Register Name: Access Type: 31 --23 --15 --7 --- PS_CR Write only 30 --22 --14 --6 --29 --21 --13 --5 --28 --20 --12 --4 --27 --19 --11 --3 --26 --18 --10 --2 --25 --17 --9 --1 --24 --16 --8 --0 CPU * CPU: CPU Clock Disable 0 = No effect. 1 = Disables the CPU clock. The CPU clock is re-enabled by any enabled interrupt or by a hardware Reset. 111 SF: Special Function The AT91M40400 provides registers which implement the following special functions. * Chip identification * RESET status * Protect Mode (see Protect Mode on page 37) SF User Interface Chip ID Base Address = 0xFFF00000 Table 14. SF Memory Map Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Register Chip ID Register Chip ID Extension Register Reset Status Register Reserved Reserved Reserved Protect Mode Register Name SF_CIDR SF_EXID SF_RSR ------SF_PMR Access Read only Read only Read only ------Read/Write Reset State Hardwired Hardwired See register description ------0x0 Chip ID Register Register Name: Access Type: 31 EXT 23 22 ARCH 15 14 NVDSIZ 7 0 6 1 5 0 4 3 2 VERSION 13 12 11 10 NVPSIZ 1 0 SF_CIDR Read only 30 29 NVPTYP 21 20 19 18 VDSIZ 9 8 28 27 26 ARCH 17 16 25 24 * * VERSION: Version of the chip This value is incremented by one with each new version of the chip (from zero to a maximum value of 31). NVPSIZ: Non Volatile Program Memory Size NVPSIZ 0 0 0 0 1 0 0 1 1 0 Others 0 1 0 1 0 0 1 1 1 1 Size None 32K bytes 64K bytes 128K bytes 256K bytes Reserved 112 AT91M40400 AT91M40400 * NVDSIZ: Non Volatile Data Memory Size NVDSIZ 0 0 Others 0 0 Size None Reserved * VDSIZ: Volatile Data Memory Size VDSIZ 0 0 0 0 1 0 0 0 1 0 Others 0 0 1 0 0 0 1 0 0 0 Size None 1K bytes 2K bytes 4K bytes 8K bytes Reserved * ARCH: Chip Architecture Code of Architecture: Two BCD digits. 0100 0000 AT91x40yyy * NVPTYP: Non Volatile Program Memory Type NVPTYP 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Type Reserved `M' Series (Mask ROM or ROM less) `C' Series (Programmable Flash through Parallel Port) `S' Series (Programmable Flash through Serial Port) Reserved * EXT: Extension Flag 0 = Chip ID has a single register definition without extensions 1 = An extended Chip ID exists (to be defined in the future). Chip ID Extension Register Register Name: Access Type: SF_EXID Read only This register is reserved for future use. It will be defined when needed. 113 Reset Status Register Register Name: Access Type: 31 --23 --15 --7 SF_RSR Read only 30 --22 --14 --6 29 --21 --13 --5 28 --20 --12 --4 RESET 27 --19 --11 --3 26 --18 --10 --2 25 --17 --9 --1 24 --16 --8 --0 * RESET: Reset Status Information This field indicates whether the reset was demanded by the external system (via NRST) or by the Watchdog internal reset request. Reset 0x6C 0x53 Cause of Reset External Pin Internal Watchdog SF Protect Mode Register Register Name: Access Type: Reset Value: 31 SF_PMR Read/Write 0 30 29 28 PMRKEY 27 26 25 24 23 22 21 20 PMRKEY 19 18 17 16 15 --7 --- 14 --6 --- 13 --5 AIC 12 --4 --- 11 --3 --- 10 --2 --- 9 --1 --- 8 --0 --- * * PMRKEY: Protect Mode Register Key Used only when writing SF_PMR. PMRKEY is reads 0. 0x27A8: Write access in SF_PMR is allowed. Other value: Write access in SF_PMR is prohibited. AIC: AIC Protect Mode Enable 0 = The Advanced Interrupt Controller runs in Normal Mode. 1 = The Advanced Interrupt Controller runs in Protect Mode. See Protect Mode on page 37. 114 AT91M40400 AT91M40400 Document Revision History Table 15. Revision History Revision A B Date June 1997 June 1998 Major changes to Revision A. Minor changes to Revision B. All changes are marked with a change bar. They are as follows: EBI: Added more detailed description of External Wait (page 16). AIC: Added section describing new Spurious Interrupt handling (page 37) and new Protect Mode (page 37) and corresponding registers (pages 47 and 114 respectively). USART: Expanded Transmit Break description and modified Receive Break description (page 69). Changes C Feb 1999 115 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. ARM, Thumb and ARM Powered are registered trademarks of ARM Limited. ARM7TDMI is a trademark of ARM Ltd. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 0768C-10/99/0M |
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